Manesh Patel Email & Phone Number

Austin, Texas, United States

Austin, Texas Area

• Automation Flows: Setup automation flows for SPARC microprocessor development. Also setup automatic regression at team level test cases. Created batch mode regression for Cadence SKILL GUI such that it does not require user intervention. Flows were written in TCL, Perl and Python and TCSH.• Extract: Lead/developed C++ based application to calculate interconnect RC using wire models. Extracted RC parasitic is used by down stream tools for timing analysis and buffer insertion. • MultiVt: Lead/developed C++ based gate VT swapping application to optimize timing and power. What-If analysis of VT swap and incremental timing impact. Included various cost functions to decide order of gates to swap or perform blanket swap.• Icopt: Development team member on C++ based interconnect analysis application for signal integrity. Implemented polarity aware buffer removal and insertion algorithm and used Verplex to verify that logic has not been inverted.• DGLG: Developed SKILL GUI based application to automatically generate layout based on certain template criteria for mask design team. Auto-generated layout is DRC aware. Created GUI with various base metal layer options, placement replay, power grid generation and routing.• Wide Bus Router: A C++ based bus router with TCL GUI interface to ICC to route buses. Thru TCL GUI, users can provide constraints, route guides on ICC. Bus routes are displayed on ICC gui for immediate feedback to the user.• BuildMeister: Responsible for managing source code repository of team branch in SVN. Follow build process to ensure new code delivery in team branch did not break anything before propagating changes to main trunk. Keep team branch in sync with trunk and setup and monitor regression for our team and patch patch process and bug/enhancement tracking with Bugzilla.

Austin, Texas Area

Sparc Microprosessor - CAD/EDA development Team. (Same job description as Oracle).

Austin, Texas Area

• Firmware engineer responsible RAS (Reliability, Availability and Serviceability) aspect of firmware on IBM’s pSeries (PowerPC) servers. Developed CPU and Memory Gard methods to dynamically disable faulty processor or memory dimm so that they are not available for OS to use. Firmware interacted with VPD and NVRAM.• Developed a surveillance technique to monitor overall heartbeat of the system. Patent was granted for this method of surveillance.• Worked on bring-up activities of IBM’s pSeries (PowerPC) servers to prepare for GA. Interacted with various functional teams to identify and resolve bring-up issues expeditiously as firmware team was in the critical path of GA.• Worked as an EDA engineer in design automation team to develop and maintain C/C++ based applications such as extraction, RC delay that are needed for timing and noise analysis for IBM’s PowerPC microprocessor design. Also developed C/C++ based engines to verify PowerPC design consistencies for unit level timing analysis.• Deployed IBM’s LoadLeveler application for batch processing, jobs queuing and resource sharing. Setup automatic monitoring of central manager server, batch job queues and paging of support personnel.