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• Imported Verilog netlist, Read SDC, TLU+ files • Performed Sanity check• Floorplan: Used source file for IO Port locations and Boundary. Provided core 2 IO boundary, Placed Macros and fixed Macros and IO ports. Derived PG connection created power straps for nets VDD, VSS and pre route standard cell rails, performed cut rows near Macros.Add End-Cap cells Tap cells and set attribute fixed true. Inserted buffers for all I/O ports. Created placement blockages (Hard, Soft), Create… Show more • Imported Verilog netlist, Read SDC, TLU+ files • Performed Sanity check• Floorplan: Used source file for IO Port locations and Boundary. Provided core 2 IO boundary, Placed Macros and fixed Macros and IO ports. Derived PG connection created power straps for nets VDD, VSS and pre route standard cell rails, performed cut rows near Macros.Add End-Cap cells Tap cells and set attribute fixed true. Inserted buffers for all I/O ports. Created placement blockages (Hard, Soft), Create placement and legalized placement and Verified Cell density, Pin density, Module placement. Placement utilization, Congestion report.CTS: Defined the routing rules width and spacing (layers and width), applied routing rule to clock nets, specified CTS buffers used for optimization.Routing: Created path groups, Defined routing layers for routing, set timing driven true for routing. Show less