Innovation Management, Technology Partnerships, Startup Investments

Leading technology Innovation, Incubation and startup Investment programs of the University.

Scouting startups, designing and running startup incubation, acceleration and investment programs.

Business DevelopmentCompetitive IntelligencePreparing and building patent portfolio of start-upsPerforming patent portfolio due diligence and transactionsPreparing marketing documents for portfolio saleAssessing market size of technology areas

Operations Management and Business Process ManagementManagement and execution of various projects related to Intellectual Property including: • IP Asset Management, Patent Portfolio Analysis, Valuation & Rating, Technology/Patent Landscapes, and Technology Market Research Reports; • Invalidity and Infringement Study, Freedom to Operate Search, patentability search; • Patent Drafting & Prosecution; • IP Commercialization, Patent Licensing, Patent Enforcement, Evidence of use (EoU) charts • Competitor Watch, Competitive Intelligence; • Patent Data Management, Visualization and Business Intelligence using Tableau; and • Strategy against Cease & Desist Letter.Mentoring fellow analysts, ensuring revenue targets are metPreparing monthly Management Review ReportsActively involved in information security compliance ISO 27001:2005

● M8S8 CapSense Express Lead Product Engineer for M8S8 CapSense Express, a part of M8S8 (M8C Harvard Architecture Microprocessor on 130 nm Technology) Programmable System on Chip family of products. Successfully delivered the TR1, PR1, MFRB, Manufacturing Plan and PR2 PE deliverables. Responsibilities included:•Pre and Post Silicon Validation, Device Characterization, Micro Probing and bench tests, design evaluation and setting datasheet limits.•Manufacturing Plan and QTP Development.•Unit Cost Breakdown Analysis and New Product Plan (NPP) update.● Silicon Characterization on 28 DIP packaged PSoC devices; SEEPROM (Cypress & competitor parts) on Advantest ATE Platform T5581 and T5362 on: I2C, SPI, MWR interface and 1Kb to 16Kb sizes.● E-test plots, Sort Yield data Analysis and Bin Wafer Maps Study for Conditional Qualification for nvPSoC● Trained on NexTest Tester Platform by NexTest Corporation; Advantest T5581 and T5362.● Integrated Development Environment (IDE) Evaluation between Cypress’ CyDesigner (PSoC Creator), Microchip’s MPLab and Freescale’s CodeWarrior.

Worked on System C, Verilog, VHDL, C/C++, Specman Elite and E Hardware Verification Language.

Patent Prosecution