My background is grounded in a strong foundation of physics and mathematics, fueling my passion for engineering. I have a deep interest and knowledge in microarchitecture, computer architecture, and RTL design, along with practical experience in developing HLS tool for generating verilog IPs with Axi interfaces. Furthermore, my expertise extends to electrical engineering, encompassing digital and analog VLSI design, semiconductor devices, power electronics, and a basic understanding of Design for Testability.