Experienced RTL Design, Simulation and Verification ProfessionalSpecialties: RTL Design in VHDL/VerilogReference Model development, VHDL/VerilogFunctional and Gate level Simulation with SDF and STARTL Verification using Verilog/System VerilogDirected or Constrained Random TB developmentOOP, OVM/UVM and SV AssertionsEDA Tools (Mentor, Synopsys VCS and Cadence NCSIM)Scripting Languages (Perl, Makefiles)