11 years  of Analog, Serdes, Custom layout expertise in  3nm/5nm/7nm/14nm/16nm  FINFET and 20/40/65nm  technologies.Good knowledge and implementation of analog layout techniques such as device matching,noise isolation,shielding,EM,IR , antenna,latch-up and ESD prevention techniques.Experience in layout of blocks such as High speed Serdes,  DAC, RTC,  amplifiers and power management blocks such as LDO, resistor dividers, DDRIO,clock circuits and standard cells.Experience in macro level floor planning, power planning and critical analog  signal planning, chip level clock routing and hit points/routability enhancement in standard cells in finfet and planar technology.Experience in DRC, DFM, LVS, ERC, EDRC, DRC plus, Antenna, parasitic reduction, EMIR fixes with TOTEM understanding and post layout extraction fixes.Good hands on experience in Cadence  Virtuoso XL  features such as modgen, cloning, annotation browser,etc.Good at debugging complex LVS errors.Good understanding  of deep sub micron  issues such as LOD, WPE.Good verbal and written communication skills.Good at problem solving, logical thinking and aptitude.Mentored freshers  in layout  concepts and virtuoso tool.