• Developed the company’s first simulation model of the hardware and firmware power management unit using the Simics platform (C++, Python), enabling customers to test power management firmware alongside OS, BIOS, and other system software. This initiative enabled firmware pre-manufacturing and pre-deployment testing in a full system simulator for the first time.- Led a team of seven engineers in developing the model of the management unit from the ground up, which included onboarding them in Simics C++ and Python development, overseeing code reviews, facilitating MOB programming sessions, mentoring junior engineers, and writing technical documentation.• Translated hardware components from specification and RTL into software using C++, Python and Ruby, to facilitate the integration of the models into the larger system simulators used in pre-silicon validation.• Validated embedded power management and system-on-chip control firmware for CPU products, ensuring reliability and performance in pre-silicon environments.• Owned the validation strategy of major client-facing SOC debug features, including the design of the test environment, definition of architectural specifications, and development of hardware simulation components.• Developed a code generation tool to translate architectural feature specifications into firmware source code and validation collateral, reducing bug fix turnaround time from weeks to hours and simplifying feature tuning by enabling seamless integration of specification changes and bug fixes into firmware and test suites without developer intervention.• Led the development of a code generation tool that streamlined the creation of checkers for sequential firmware-hardware interactions, which reduced onboarding time for new validators.•

• Designed the physical layout of several IP I/O cells with digital and analog components that are part of Intel’s Axxia networking ASICS. Implemented the layout of cells, including low voltage, high voltage and extra high voltage nets, in Intel’s 10nm process.• Responsible for the physical implementation of IP, starting from schematic netlist, floor-planning, cell placement, route, fill, DRC, LVS, reliability verification and simulation, and sign off.

• Worked in the development of pristine graphene foams and thin films for applications in electronic devices. • Enhanced procedure to manipulate and fabricate graphene foam monoliths through freeze-casting. • Developed and tested gel electrolyte super-capacitors with graphene foam based electrodes. • Designed and characterized a silver nanoparticle-graphene nanotube composite inks for printed electronics.• Produced and characterized electronic and energy storage devices, printed using solution-processed carbon nanomaterial inks.Advisor: Prof. Mark Hersam