Senior Digital Designer with significant experience in VLSI circuits. Problem solver, driven by improving the quality and robustness of the RTL. Member of the PCIe team for more than 7 years, acquired the capability to specify and implement RTL meeting systems requirements (PCIe Spec and/or customer additional requirements) following the best practices in writing code - coding style and linter analyses. As Tech Lead, was responsible for coordinating a small team and planning project tasks. Experienced supervision of youngest peers and students in internships and Master’s thesis. Nowadays, as an SoC designer, he is working close to the BE team, diving deeply into Formal Verification, and being the person in touch for any Formal Verification initiative in the team.Tech Skills• HDLs: System Verilog HDL, Verilog HDL, SVA;• Programming Languages: C, C++ Scripting: TCL, Python• Software Packages: DesignCompiler, Spyglass, VCS, DVE, Verdi, VC Formal, ModelSim, Xilinx ISE, Xilinx Vivado, Matlab.My areas of interest include:• Digital VLSI Front-end Design/Verification• Formal Verification• Processor Micro-architecture