* Developing compute engines that run at 100GHz+ at standard operating conditions and provide technological path to reach 1.0THz speeds, while the current performance limit is at about 9.6GHz which is only achieved under laboratory conditions.* Joined RISC-V International as an individual member and working on making technical contributions to the RISC-V, this included learning the Sail language to describe the RISC-V ISA. Additionally, developed a modern version of the "Opcode Map" using a spreadsheet to visually see ALL the RISC-V opcode and more importantly the gaps and donated the spreadsheet to the RISC-V foundation and community at-large!* Developing a novel Video Game Application using the MonoGame platform and in the process ended up learning C# as well.* Developing technology to bring together video gaming together with AR/VR using remote control devices by leveraging the ESP32-WROOM and ESP32-CAM IoT modules.* Developing technology to accelerate both the inference and the training processes for ANN, RNN & CNN types of Neural Networks Systems via novel digital logic based hardware architectures.* Providing an award-winning STEM workshop to Portland-Metro area schools to help expose K-12 students to engineering well before they go to college. While exposing them to all the different types of engineering, the workshop goes in depth into electrical engineering with students starting off building a simple light switch circuit to eventually building their own A.M. Radio and A.M. Radio Station from scratch! See my workshop introduction video at: https://youtu.be/KvR_VCRl14o

* Provide design and verification of digital ASICs used in laser and inkjet printer products.* Provide overall design and verification support as well.* Only after three weeks on the job, including spin-up time, caught and fixed a bug that made it into two prior chips* Just after two months verified and finished a design feature that had not been reviewed for more than two years and is not operational in the prior two chip designs.* Working as part of a VERY global team worked with a design engineer in Korea to remove two timing-loops from their design and as a result developed a method to quickly locate the source of the timing loop in RTL code.* NOTE: Due to my religious exemption from being vaccinated being rejected by the company, I got administratively terminated and really wanted to stay much much more longer than just 8 months, but I had 8 rather productive months! ;-)

* Reviewed and documented the AWS Cloud FPGA workflow, which included resolving I.T. infrastructure issues, particularly challenges encountered with regard to VNC connections.* Worked on integrating the current in-house FPGA shell wrapper with the AWS Cloud FPGA (Xilinx Alveo U200) workflow targeting Video and A.I. FPGA based code acceleration.* Independent of the FPGA being in the cloud, successfully generated PCIe bus transactions from the FPGA to both read and write the system's Host memory, which involved converting the Host's allocated memory's virtual address into a physical address, which was then provided to the FPGA. This effort included RTL coding as well as writing Host code in C, as well as working to create "huge" continuous page allocations, i.e. greater than 4KB pages, via mmap().

Continued work on a novel A.I. ANN/RNN/FNN/CNN (xNN) training algorithm and finally achieved a KEY technical milestone on June 12, 2019 that involved validating the algorithm with better than expected results!!! For those technical folks out there, we found the FFT version of the DFT used in DSP analysis for A.I. training! The plan is to provide the technology via a HaaS (Hardware-As-A-Service) business model using FPGAs to significantly accelerate the training of xNN systems for organizations who need help training their xNN systems without needing to develop or hire A.I. experts!

* Learned first hand about working at a LARGE Corporation* While having already experience the beauty of SCRUM concepts at a prior job, discovered that there was a formal name to the practice, i.e. SCRUM, but it was only partially implemented and I STRESS the word partially! ;-)]* Discovered the Agile programming practices (TDD, Pair-Programming, MOB Programming, Clean Code, etc.) and applied them via real hands-on experiences* Became a strong advocate for Agile concepts to be applied across ALL engineering and non-engineering disciplines!!!* Also helped out in the validation of SoC products as part of the DDG group.

Performed Full-Chip, including Gate-Level, pre-silicon validation of a HPC networking switch (APR). Since this effort involved gate-level simulations of the critical Reset & Clocking block and other blocks, I also developed methods to carry out an efficient hybrid gate-level & RTL simulation at full-chip level. Additionally worked to resolve issues with various vendor IP and developed, as well as documented, more automated methods to help out with project level issues with warnings and errors.

Re-vamped previous CSI-2 VIP integration efforts which also involved debugging the VIP! ;-) During that effort developed a CSI-2 C-PHY lane analyzer (for RX & TX) that would then become the basis for a C-PHY model that got delivered to customer as a C-PHY behavioral model! Successfully performed two separate customer specific CSI-2 system level IP integration efforts for two separate major tech industry customers.

Responsible for the mapping of the company's 3rd generation 2D-to-3D video conversion algorithm into an FPGA and shortly there after into an ASIC which will provide real-time conversion of any 2D video source into 3D that can drive 3D TVs that require no glasses!*** CAREER HIGHLIGHT ***: Aside from totally geeking out on video and image processing at VEFXi, I developed my first from scratch script ever, i.e. I usually just tweak other peoples' scripts, which was written in Python, but it was no ordinary script since it took a JSON based abstracted description of an Artificial Neural Network (ANN) and generated the necessary RTL code to implement the ANN in a FPGA!

* Integrated OVM/UVM based SystemVerilog Verification IP (VIP) for both MIPI-DSI Host and Peripheral IP* Developed PCIe DMA controller tests along with setting up nightly regressions.* Worked on automated register RTL code generation and other intrastructure processes

Carrying out design and verification work for the J750 testers, particularly the DC control subsystems, parametric testing unit and the connection manager.

Working on the development of a portable ultrasound system.

Initially developing a novel MAC IP block that is a highly enabling technology for standard or custom communication packet protocols.Since June 2010, the MAC IP development has been on hold and the focus has shifted to developing an innovative fitness monitor system that will provide full fitness analytics such as distances (in all dimensions), simple/complex rep counting, heart rate, oxygen level and body core temperature without GPS technology, while being usable during any fitness event or exercise including swimming (in pools or open water). With the ability to easily expand to team sports too.

Exercising different modules and aspects of the ARM based PSoC silicon devices from Cypress. Particularly the Full-Speed USB module and special purpose GPIO pins.

MAC/SOC Digital Designer for UWB WiMedia standard. Continuation of work done at Avnera, but working against a standard and not limited to just audio.

Responsible for the design, implentation and integration of an embedded computer system that is designed and architected from scratch using a combination of purchased IP, In-House IP and custom IP. The computer system is to be integrated into a single chip SOC that also incorporates RF and Analog circuits.*** CURRENT CAREER PINNACLE *** Started on a 2nd project about 7 months after starting work for Avnera, the 2nd project was a much higher priority project. From my personal involvement on the "2nd" project to time we got silicon in hand was just 4 months with 1st pass success on a wireless SOC design that contained digital, DSP, analog and RF design blocks on a single die; up and full running in less than a week after getting silicon in hand.

Worked on Microprocessor design. The company is also doing software and system-on-chip development to be used in a complete solution system for our customers. The end product WILL define a new product that is on the same scale as the personal computer (PC) that helped to define the 70's & 80's. A product that will help to define the 21st century in the same pioneering manner as the PC did in the past.

Worked on the microprocessor design team for ARM Core to added out-of-order execution. Particularly on the instruction execution block and the commit/retirement block. Also wrote ARM assembly code to help with debugging of the core's design. The job was in Cary/RTP, NC not San Diego.

Worked on the hardware debugging logic for 16F877 and helped with debug of the 18F core.Worked on the initial design of the dsPIC core. Particulary the PC, Instruction Register, Instruction Sequencer, Instruction Decode, Looping Control and Status Register logic.Also worked to take the product to production by taking on test engineering roles using the Teradyne J750 tester.

Started off in the Government side of Harris Corp. (GASD) then moved to the Semiconductor side. The Harris Semiconductor group would separate off and become Intersil.Worked on the design of ASICs, PCB/PWBs, and FPGAs. In application role worked with customers to resolve issues with Video Encoders & Decoders, Hi-Speed A/D & D/A converters.It was while working at Harris Semi/Intersil that I initially got some hands-on exposure to DSP & RF design concepts.

This was a VLSI design job that I got thanks to my VLSI design class instructor (Wei Li) at NCSU. This summer job would carry on into being a part-time job in the fall until graduation.I worked on the design of standard cells for a clocked Low-Voltage Differential Signal (LVDS) library that provided logic that produced complimentary outputs while providing an area savings over simply using duplicate copies of the CMOS logic. This was a NSA funded project. I never got to meet any of the NSA folks...oh well. ;)

The lone "technician" in a medical device start-up, while I was still in high school, that initially developed a compressed air (a CO2 stand alone container) assisted syringe. This syringe was used to pump a very viscus compound into a patient's body so that blockages could show up on X-Rays. The company would then broaden its offerings and manufacture biopsy forceps and laproscopic instruments. In 1992 the company would have a rather successful exit and got acquired for $175M. My experiences ranged from developing mechanical prototypes using lost wax injection molds and doing some basic AutoCAD drawings, i.e. 2-D only, to eventually moving into machine validation, database development/migration/support and PC support. I would decide to use my proceeds from the successful exit to finish up my degree. It was certainly a nice journey with lots of learning about both business and engineering. This experience drove me to also minor in business.

This opportunity started off as a co-op experience while I was in high school, but initially I only got high school credit for the experience. That would change after I graduated from HS. Aside from working full-time over the summer after graduation, I worked part-time, via Fedex, during my first year of college.I was responsible for writing the motor control firmware for a medical device that was the equivalent of the roto-rooter for cleaning plaque buildup in veins and arteries which limited blood flow. My initial involvement with the company was when it was just Theratek...a novel medical device start-up. It would eventually get bought in the fall of 1990 by Dow-Corning Wright. It was a modest exit, but it certainly could have been worse. Still a great learning experience and yes, I did time-slice myself with working at Symbiosis...there was still the weekends right and I was rather young back then. The people at both companies made ALL the experiences an overall GREAT experience for me.