Maor Carl Email & Phone Number

- In-depth design of the VHDL language with an emphasis on code for synthesis and performance.- Simulation includes the use of TEXT IO.- Work and in-depth acquaintance with key basic components in FPGA - FIFO, BRAM, DSP, PLL.- Working with DSP components - implementing a divider using a multiplier, root calculation, standard deviation calculation.- Understanding of internal clock structure inside the FPGA. Ability to analyze timing reports, locate planning bottlenecks, solve timing problems and use constraints.- Implementation of practical projects that include - simulation and synthesis for example: collecting a histogram.

Education record

Fpga Design

Comprehensive FPGA development course, learning about VHDL software, knowing the internal structure of the components, personal project.