Marc Bennett Email & Phone Number

Austin, TX, US

Digital integrated circuit (FPGA/ASIC) design and verification (UVM) for medical devices, IoT, networking/communications, image processing, pipeline inspection.

Draper, Utah, US

Responsible for FPGA, PCB, Mechanical, Embedded Software, Communications

Draper, Utah, US

Digital ASIC/FPGA designer and co-leader of ASIC group

DisplayPort IP design

San Jose, CA, US

FPGA manager for highly productive San Jose, Shanghai, and Austin-based team for Industrial IoT projects, primarily focused on industrial networking IP and platform development for industrial-grade Ethernet switches, routers, and wireless access points. Our FPGAs (22) provide support for multiple redundancy protocols, determinism, network timing, NAT.

Pullman, WA, US

Making electrical power safer, more reliable and more economical.

San Jose, CA, US

• Ethernet Technology Switching Group. FPGA design: Network Address Translation (NAT) and IEEE1588 PTP protocol implementation in a space/cost/power-constrained industrial Ethernet switch.
• FPGA-based "bump-in-the-wire" NAT implementation architected from scratch covering entire protocol stack from the data link layer to the application layer. Transparent NAT support for IP, ARP, TCP, UDP, ICMP, FTP, SNMP.

• Engineering Design Services and Technology Commercialization Consulting
• Design Services - primarily FPGA design
• Factor Analysis/Principal Component Analysis for Oil Exploration lease to provide an optimum predictive model for drilling success using 30 different remote sensing variables
• Technology Commercialization – primary and secondary research to determine commercialization potential for wide range of technologies culminating in 30-80 page reports with advice for commercialization strategies..

• PHY/MAC design for home/access networking IC
• FPGA design: ground-up implementation of physical layer device for a revolutionary fully-meshed any-wire transport technology for an early stage start-up. Applications are “to the home’ and “in the home” networking.
• Clock recovery: 3 generations implemented involving CORDIC, NCO, moving average filter, pilot tone weighting, and sliding Goertzel. Excellent jitter and wander realized, resulting in optimum system performance.
• Major blocks: FFT/IFFT, framing, clock recovery, pre-emphasis, in-band command and control channel, training and equalization, bit load calculation, link state machine, symbol mapper and demapper, convolutional and.
• Extensive built-in control and debug implemented using a combination of an embedded processor, custom logic analyzer interface, traffic disruptor, channel emulation, and parameter control.

San Jose, California, US

• FPGA design: Altera and Xilinx implementations of video IP for HD videoconferencing platform. Full responsibility for design, IP evaluation and integration, timing closure, simulation, and verification in hardware.

San Jose, CA, US

• FPGA, ASIC, PCB, and system level designs for carrier class communication transport systems. Mutli-site management and project leadership experience. TDM, SONET, Ethernet, Fibre Channel/FICON, and carrier class optical.
• Hardware Lead for SAN extension interface for the ONS15454, the industry leading metro optical transport platform. Managed board design and FPGA teams and contributed technically to both. Fibre Channel/FICON GFP-T.
• Managed team of board level and FPGA engineers and technicians to successful and on-time completion of industry first private line Gigabit Ethernet SONET transport card. Contributed as engineer at the board and FPGA.
• FPGA/board design of enhanced DS3 card for Cerent 454: extended capability of existing DS3 card to include complete DS3 performance monitoring, J1 path trace, PRBS transmission/detection, and automatic frame format.

Espoo, Southern Finland, FI

• ASIC/FPGA experience: 4-way Interleaved Reed Solomon encoder/decoder, SONET framing, 4 dimensional Trellis encoded modulator/demodulator, microcontroller interfaces, DS3 processor, DS3 errorless switching.
• PCB design: DS3/EC1, DS3/E3, and DS1/E1 line cards for fixed wireless transport systems, SONET orderwire/relay interface, LBO, fan card, audio interface, ASIC emulators for fixed wireless transport systems.

M.S., Technology Commercializtion

B.S., Mathematics

M.S., Electrical Engineering

B.S., Electrical Engineering