Marc Padilla Email & Phone Number

Salt Lake City Metropolitan Area

Slc, Ut

Communications analysis, development, and testing of high rate data links and modems

2010: Rapid Reconfigurable Computing (RC) Development TechniquesThe goal of this project is to go from schematic capture design of a radio to a working design in hardware in a matter of seconds. With Xilinx ISE, MATLAB System Generator, and Java, our four person team has created an alternative end-to-end flow that reduces FPGA compilation time between design modifications.2009: Reuse Tools for RC DesignCreated library of parameterized VHDL blocks used to rapidly prototype various radio types on an FPGA board. As Project Leader, oversaw two undergraduates during design, debug, and verification stages. Demonstrated rapidly prototyped radio designs on actual hardware.2008: Reliable RC Digital Signal Processing (DSP)/Communications SystemsDesigned, tested, and debugged a PLL-based QPSK receiver using MATLAB System Generator. Final design tested on LANL’s CFE engineering model and intended for actual satellite. Generated design fault-sensitivity data using custom fault-injection board.

Write programs in various languages (Unix scripting/AWK, PHP, Perl) for interaction with the library catalog and MySQL databases.

Ms, Electrical And Computer Engineering

Work with Dr. Nelson/Dr. Rice researching Digital Signal Processing on FPGAs. Thesis: FM Demodulators in Software-Defined Radios.

Bs, Computer Engineering

Activities and Societies: Tau Beta PiAugust 2009 Graduation