Marc Eden Email & Phone Number

• Significant contributions to mutliple FPGA projects including:o Developed RTL and SystemVerilog testcases for digital video rasterizer block. o Verification of video interface FPGA – testcases and simulations in system.
• Coached FPGA team leaders and group supervisor, guiding team towards best development practises, and… Show more
• Coached FPGA team leaders and group supervisor, guiding team towards best development practises, and project, team and personal management tactics. Show less

o Managed IC, embedded SW, FPGA and HW designers, completing on a variety of ExtremeUSB projects including box products, IP offerings, FPGA partnerships with other companies, and ASIC design.o Provided technical guidance on FPGA, ASIC and IP design work. o Technical liaison with ASIC vendors, IP clients, and FPGA customers. o Completed handoff of most.

o Sport = Cell-basestation SoC in 90nm providing signal AD/DA and programmable DSP for digital pre-distortion, wave-shaping and adaptive PA biasing. o Balanced fixed logic, 3rd party CPU configuration, and HW DSP elements for a cost-effective and high performance design.o Developed top-level architecture to bind high-performance DSP logic with a MIPS34k.

GP Processor Design Leader - Subsystem and IP o GP = 500MHz 90nm low-cost, general-purpose SoC, targeted at high volume markets.o Completed specification, partitioning, and high-level design of multiple subsystems and oversaw their implementation – system bus, Ethernet, USB, flash interface, and DMA. Evaluated, selected, and managed use of 3rd-party IP.o.

ILS Design and Program Leadero ILS = 6M packet/s IPv4 edge-router-on-a-chip, providing datagram parsing, next-hop lookup, microflow classification, and DiffServ functions implemented in a 0.18um embedded SDRAM CMOS process.o Transformed a challenging system spec into a product comprising fixed-function logic, integrated MIPS CPU, embedded firmware, and.

• Project leader for 3-channel, 45 MHz FIR-based, image resizing chip in 0.8um CMOS. Supervised, scheduled, handled fab liaison modeled and completed block-level design on time and to specification.
• Crucial contributor for two other image resizing chips including functional modeling in C, schematic capture, simulation, place-and-route, DRC/LVS/LVS, test vector generation.