Marcus Weber Email & Phone Number

Twenty years of ASIC architecture, design, and verification experience in the areas of SoC and wireless modem chips. Knowledge and experience with ASIC design flows from architecture and design to back-end physical design including test methodologies, and initial silicon bring-up and debugging. Architecture and implementation of Wi-fi, Wi-max, and custom OFDM modems. Integration of processor IPs, busses, and peripherals.Extensive experience in SoC architecture, bus architecture, ARM IP integration, hardware security, low power design and implementation of DSP algorithms in hardware. I have used multiple Altera and Xilinx FPGAs. I have written software drivers and ASIC test code in C.Experience with integration and test of high-bandwidth, wireless communication systems including RF integration and debug, MAC layer software integration and test, and system performance and debug.Languages include verilog, VHDL, C, MATLAB, perl, and python.I've debugged issues including rtl bugs, software bugs, timing problems, testbench bugs, compiler bugs, simulator bugs, DFT insertion bugs, ASIC library bugs, and board level noise, power, and clock problems.

Listed skills include Asic, Soc, Digital Signal Processors, Embedded Systems, and 13 others.