Marcus Wei Email & Phone Number

Munich, DE

 Managed ASIC backend for all projects, with responsibilities including resource allocation, schedule and milestones tracking, coordination of engineers across multiple sites, and collaboration with frontend design teams. Owned and implemented physical design of the top-level for all projects. Core design challenges included synthesis and floorplanning.

Santa Clara, CA, US

 Project manager for all local turnkey projects. Responsible for resource budgeting, schedule and milestones tracking, cross-department cooperation, coordination of engineers across multiple sites, and general communication with customers. Acting technical lead for some local turnkey projects. Either directly implemented or guided top-level design for.

San Jose, CA, US

 Led multiple teams as the technical lead and project manager for many projects, sometimes 2-3 projects simultaneously.  Supported Tier 1&2 customers, communicating directly with all levels ranging from engineers to senior directors and making sure customers were always comfortable and knowledgeable about the state of the project. Coordinated multiple.

San Jose, CA, US

 Acted as technical lead and project manager for many projects, working with the customer and the engineering team to deliver the project on schedule. Optimized and automated our approach to CTS, replacing more manual implementation to ensure quality of clock tree with lower latency and better region placement. Major CAD contributor who overhauled the.

San Jose, CA, US

 Owned multiple blocks on multiple chips, spanning many different technologies ranging from 130nm TSMC to 28nm Samsung. Developed a new syntax for encoding a proprietary length-based buffering flow, cutting down on redundancy and improving reliability. Also developed several algorithms in this flow to automate distribution of buffers and partitioning of.

Sunnyvale, California, US

 Wrote physical design flows and implemented PHYs for PCIE and USB IP from netlist to GDS closure.

Santa Clara, California, US

 Owned several partitions of different GPU chips, bringing each one from synthesis to GDS closure.

Santa Clara, California, US

 Aided in the development and enhancement of AMD’s physical design flow using a combination of csh scripting, Perl/Python scripting, SQL scripting, and EDA tool Tcl scripting for flow targets.

Santa Clara, California, US

 Generated, organized, tracked, and checked quality of various standard cell and macro libraries.

Master'S Degree, Electrical And Computer Engineering

Bachelor'S Degree, Electrical And Computer Engineering