Marcus Wei Email & Phone Number

Munich, De

 Managed ASIC backend for all projects, with responsibilities including resource allocation, schedule and milestones tracking, coordination of engineers across multiple sites, and collaboration with frontend design teams. Owned and implemented physical design of the top-level for all projects. Core design challenges included synthesis and floorplanning, power domain definition and infrastructure construction, SDC development and integration, bump array and padframe creation, clock balancing and timing closure, LEC debug, and physical verification. Performed all the interviewing and hiring for Physical Design and DFT positions. Wrote tutorials and guides on specific aspects of Physical Design, such as clock balancing, bump mapping, and RDL routing. Created the tapeout signoff checklist, consolidating manual checks, visual verification, and corner cases for physical design, DFT, RTL design, verification, package design, and board design. Did assessments of various technology nodes and their PPA (Power, Performance, Area) metrics, cost, and viability with our design needs. Worked closely with 3rd party package design teams to develop the flip chip package, and interfaced with 3rd party PCB designers for the test board. Initiated research for Operations by looking into qual plans, testing houses, and manufacturing schedules and costs. Aided chip bring-up efforts by running test sequences through an FPGA, tracked current and power consumption for different modes, manually probed packaged and naked dies for resistance values and the presence of diodes. Searched for and contacted a dozen FIB (Focused Ion Beam) service providers to fix a faulty test chip. Crafted a solution proposal and gathered feasibility studies, preparation samples, and cost quotes.

Santa Clara, Ca, Us

 Project manager for all local turnkey projects. Responsible for resource budgeting, schedule and milestones tracking, cross-department cooperation, coordination of engineers across multiple sites, and general communication with customers. Acting technical lead for some local turnkey projects. Either directly implemented or guided top-level design for most projects, and provided targeted trouble-shooting across the entire spectrum of physical design, such as clock balancing, power structures, IO interface, LVS, and timing. Architected the internal CAD infrastructure used for all local turnkey projects, a parameter-template hybrid flow builder designed to retain engineering knowledge across multiple projects and increase user efficiency and versatility. Wrote custom scripts and flows that are independent of EDA tools to perform clock and connectivity tracing, organize and implement block pins, and map bumps to pads in flip-chip designs. Oversaw the allocation of all local physical design and DFT manpower. Managed all the hiring for Physical Design and CAD turnkey positions.  Performed budgeting for labor/tools and wrote proposals and SOW (Statement of Work) contracts to customers for turnkey projects. Supported sales meetings with clients involving turnkey operations, providing technical insight into what made us a formidable design house. Controlled compute machine, disk space, and license allocation for each project, and maintained Unix user and group rosters and permissions. Designed a training program capable of enabling fresh graduates to become junior block-level Physical Designers. Brought in multiple generations of interns, who transitioned to fulltime engineers.

San Jose, Ca, Us

 Led multiple teams as the technical lead and project manager for many projects, sometimes 2-3 projects simultaneously.  Supported Tier 1&2 customers, communicating directly with all levels ranging from engineers to senior directors and making sure customers were always comfortable and knowledgeable about the state of the project. Coordinated multiple groups on each project to work closely with Physical Design, including RTL developers, DFT teams, Verification engineers, and Power teams. Guided the CAD team with specific tasks and development goals. Created and optimized checklist and signoff systems used to ensure a detailed level of quality at each major of phase of a project. These systems were used universally by all teams to help ensure consistent quality of results and data integrity on all ASIC Design Projects. Supported sales calls as a technical sales representative, aiding with explanations of the company’s technical strengths and other merits.

San Jose, Ca, Us

 Acted as technical lead and project manager for many projects, working with the customer and the engineering team to deliver the project on schedule. Optimized and automated our approach to CTS, replacing more manual implementation to ensure quality of clock tree with lower latency and better region placement. Major CAD contributor who overhauled the department’s global project file system with regards to how ASIC Design tech, library, and run directories were organized and shared. Mentored engineers and managers to share and disseminate personal/custom flows and scripts and consolidate them in a central repository to broaden access and understanding. Participated in a sales trip to China as a technical sales representative, to support technical sales of DDR subsystem and ASIC Design services. Leveraged Mandarin Chinese fluency for such technical sales engagements. Created technical material for Uniquify’s internal training program. Organized and taught most of the training classes for incoming generations of junior and intern engineers.

San Jose, Ca, Us

 Owned multiple blocks on multiple chips, spanning many different technologies ranging from 130nm TSMC to 28nm Samsung. Developed a new syntax for encoding a proprietary length-based buffering flow, cutting down on redundancy and improving reliability. Also developed several algorithms in this flow to automate distribution of buffers and partitioning of routable areas into manageable regions. Owned the top level of a hierarchical chip, worked with two block owners to establish new methodologies for faster timing closure and fewer top-level routing violations.

Sunnyvale, California, Us

 Wrote physical design flows and implemented PHYs for PCIE and USB IP from netlist to GDS closure.

Santa Clara, California, Us

 Owned several partitions of different GPU chips, bringing each one from synthesis to GDS closure.

Santa Clara, California, Us

 Aided in the development and enhancement of AMD’s physical design flow using a combination of csh scripting, Perl/Python scripting, SQL scripting, and EDA tool Tcl scripting for flow targets.

Santa Clara, California, Us

 Generated, organized, tracked, and checked quality of various standard cell and macro libraries.

Master'S Degree, Electrical And Computer Engineering

Bachelor'S Degree, Electrical And Computer Engineering