Marek Smoszna Email & Phone Number

California, United States

Campbell, CA, US

Palo Alto, California, US

• SRAM memory component design, memory compiler flow, timing and back-end analysis:
• Working extensively with a memory compiler to generate memory IP.
• Timing and noise analysis across process corners with Nanotime.
• Reliability analysis focusing on power grid EM & IR drop, and noise.
• Contribution to flow and methodology development.

Los Angeles, California, US

• Working on my next book and course: Distributed Dynamic Circuits and Full Swing Memory Design.
• Online course development and publication (Udemy/Linda): “Learn How to Design Electronics for Computer Systems”, 2018.
• Authored a book on dynamic circuit design entitled “Synchronous Precharge Logic”, Elsevier Insights, 2012.

Suwa, Nagano, JP

Wrote whitepapers on aspects of timing and power concerning novel oscillator circuit design & crystal manufacturing for Real Time Clock modules.

• Design environment setup, dynamic circuit design, memory feasibility analysis:
• Collaboration with IT and EDA vendors on custom design environment setup (eg. Cadence, Spice).
• Dynamic circuit design/methodology for AI specific ALU.
• Memory architecture and feasibility analysis.

San Jose, CA, US

• Lectured on “Electronics for Computing Systems”, a computer hardware design course (CMPE110):
• passive RLC networks
• Laplace transform
• bipolar circuits
• CMOS circuits
• MOS logic design

San Diego, California, US

• Mathematics work with the intent to create a better software tracking system for missing children:
• Worked with a research team leveraging and translating Navier-Stokes equations in a novel way.
• The intent was to create a better software tracking system for missing children.
• These equations were originally meant to describe the motion of viscous fluid substances.
• However there are many practical applications, and they have never been used to create a better way to find missing children.

San Jose, California(CA), US

• SRAM memory verification, design completion, timing and back-end analysis:
• Functional verification with a vector simulation flow.
• Timing analysis across process corners with Nanotime.
• Reliability analysis focusing on power grid EM & IR drop, and signal noise.
• New design planning and feasibility studies.

Santa Clara, California, US

• Nanotime timing analysis on SERDES units, focusing on CMOS PLL clock dividers:
• Considerable timing constraint and exception development for the various designs.
• Assistance in design based solutions to timing problems.
• Coordination with team members in four locations across the globe.

Santa Clara, California, US

• Standard cell design, structured datapath design, timing methodology (processor and SoC):
• Monte Carlo statistical simulations for POCV (parametric on-chip variation) coefficient modeling and methodology for Nanotime timing analysis. *
• Scripting to automate the POCV simulations and data generation for new process corners and future technology changes.
• SoC and processor core source-synchronous interface (timing across different clock domains, level shifting, and physical FIFO planning).
• Balanced level shifter design to minimize duty cycle variation for clock transmission.
• Specialized glitch gating standard cells for power reduction.

Santa Clara, CA, US

• Custom circuit design, memory & register file design, clock and noise methodology:
• Advanced register file and multi-ported bitcell design for VISC processor architecture. *
• Self-timed and frequency dependent margin analysis using Nanotime and Ultrasim.
• Local clock distribution study and clock gating methodology.
• Storage element design, including time borrowing flip-flops.
• Robust noise methodology for dynamic circuit style read bitlines, overcoming Nanotime noise analysis limitations.

Santa Clara, CA, US

• Memory design for high performance & low power ARM processor IP:
• Full swing (8T bitcell) memory design concept evaluation.
• Full swing level one data cache design (128kb banks for tag and data).
• Full swing special purpose RAM design.
• Heavy design reuse and common building block development for all 8T bitcell RAMs.
• Assistance with NOR type CAM topology evaluation.

Palo Alto, CA, US

• SRAM memories (6T & 8T), multi-cycle signaling, noise methodology for SPARC processors:
• 6T differential and 8T full swing style RAM and CAM design.
• Self-timed and frequency dependent timing margin analysis using the fast simulator XA.
• Extensive work in the area of latch based multi-cycle signaling.
• Simulation based time borrowing and timing optimization.
• Inter-unit physical route planning with the integration team.

• Redesigned IP library cells for compiler generated RAM, based on customer needs:
• This semiconductor company created high density embedded DRAM cores for applications in the networking, wireless, graphics and imaging industries.
• Worked on AIX.

Milpitas, CA, US

• Custom circuit design and verification on memory sub-blocks for MIPS processors: *
• SGI was a computer systems company that optimized the MIPS architecture for graphics: processors such as R4k, R8k, R10k.
• Most of Jurassic Park was done on SGI systems and the R4k processor powered the first Nintendo64.
• Worked on IRIX.* Note: MIPS here comes from the micro-architecture term "Microprocessor without Interlocked Pipeline Stages" – e.i. simpler hardware, more advanced compiler. This is in contrast to other RISC processors.

Certificates, Vlsi Circuit Design

Neuroscience

Leadership And Management

Computer Programming

Master'S Degree, Electrical And Computer And Systems Engineering

Exchange Programme, Electrical And Electronics Engineering

Exchange Programme, Electrical And Electronics Engineering

Bachelor'S Degree, Electrical And Computer And Systems Engineering