Marek Smoszna Email and Phone Number
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A circuit design engineer, writer, lecturer, innovator and entrepreneur in the semiconductor industry. Secondary interests include neuroscience & artificial intelligence, and the intersection of those two expanding fields. My purpose is simple: to make everyone else's life better through collaboration, education and information sharing.Leadership snapshot:• Technical lead for various design groups.• Mentor for junior engineers.• Professor at a local university.• Achieved collaboration between cross functional teams.• Strong verbal and written communication skills.• Approachable personality.• Well-traveled, understanding cultural differences and language barriers.• Team player and team builder.• Excellent recruiting skills for building the right team.• Solid decision making. I do what is right in the moment with long term objectives in mind.• Win-win and synergy mentality.On a personal level:• Time management is a habit, e.g. time blocking, urgent vs important goals, 20/80 rule.• A proactive approach to life is the basis of how I build excellent relationships.• Experience with early design tradeoffs between specification targets, risk, and design time/cost.• Detail and excellence oriented.• Learning and growth mindset.Technical snapshot:• various types of SRAM based memory design• dynamic style digital design• clock distribution• timing analysis• multi-cycle signaling• source-synchronous interface design• analog cell design (e.g. current mirrors, level shifters)• lecturing on sensor interface circuits• lecturing on ADC and DAC designs• various types of design methodology developmentInnovation snapshot:• Simple fuse programming for row redundancy (6281736, 6384665).• Monotonic CAM key driver, removed latch for faster D-Q, latch then activated with XOR.• Time borrowing FF (no dead time), using parallel pulsed latch.• Extended latch for added drive strength without adding loading.• Noise tolerant precharge logic (NTPL) with input pulldown for LU noise.• Gate driven column mux for full swing read SRAM (20140085965).• Gated keeper for full swing read SRAM.• Low gate delay scannable latch, mux removed from D-Q, duplicate latches added elsewhere.• Scannable clocked SR latch for dynamic logic and full swing read SRAM.• Active receiver for long distances between repeaters in channel routing.• Low power buffer for long wires, with self resetting loop.• Innovative design reuse.
Aril Inc.
View- Website:
- arilinc.com
- Employees:
- 17
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Senior Staff Design EngineerAril Inc.California, United States
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Course Developer And WriterAuthorCampbell, Ca, Us -
High Speed Memory Design EngineerBroadcom Inc. May 2021 - PresentPalo Alto, California, UsSRAM memory component design, memory compiler flow, timing and back-end analysis:• Working extensively with a memory compiler to generate memory IP.• Timing and noise analysis across process corners with Nanotime.• Reliability analysis focusing on power grid EM & IR drop, and noise.• Contribution to flow and methodology development. -
Course Developer & WriterAuthor Mar 2011 - PresentLos Angeles, California, Us• Working on my next book and course: Distributed Dynamic Circuits and Full Swing Memory Design.• Online course development and publication (Udemy/Linda): “Learn How to Design Electronics for Computer Systems”, 2018.• Authored a book on dynamic circuit design entitled “Synchronous Precharge Logic”, Elsevier Insights, 2012. -
Technical WriterSeiko Epson Corporation, Japan Jan 2021 - Mar 2021Suwa, Nagano, JpWrote whitepapers on aspects of timing and power concerning novel oscillator circuit design & crystal manufacturing for Real Time Clock modules. -
Custom Circuit Design ConsultantCornami, Inc. Oct 2019 - Mar 2020Design environment setup, dynamic circuit design, memory feasibility analysis:• Collaboration with IT and EDA vendors on custom design environment setup (eg. Cadence, Spice).• Dynamic circuit design/methodology for AI specific ALU.• Memory architecture and feasibility analysis. -
ProfessorSan Jose State University May 2017 - Dec 2019San Jose, Ca, UsLectured on “Electronics for Computing Systems”, a computer hardware design course (CMPE110):• passive RLC networks• Laplace transform• bipolar circuits• CMOS circuits• MOS logic design• MOS device sizing• sensors• Op Amps• basic ADC architectures• basic DAC architectures• clocking and pipelining basics -
ResearcherIt'S All About The Kids® Foundation Jan 2019 - Sep 2019San Diego, California, UsMathematics work with the intent to create a better software tracking system for missing children:• Worked with a research team leveraging and translating Navier-Stokes equations in a novel way. • The intent was to create a better software tracking system for missing children. • These equations were originally meant to describe the motion of viscous fluid substances. • However there are many practical applications, and they have never been used to create a better way to find missing children. -
Senior Design EngineerWave Computing Mar 2018 - Nov 2018San Jose, California(Ca), UsSRAM memory verification, design completion, timing and back-end analysis:• Functional verification with a vector simulation flow.• Timing analysis across process corners with Nanotime. • Reliability analysis focusing on power grid EM & IR drop, and signal noise.• New design planning and feasibility studies. -
Senior Timing EngineerAmd Jul 2017 - Dec 2017Santa Clara, California, UsNanotime timing analysis on SERDES units, focusing on CMOS PLL clock dividers: • Considerable timing constraint and exception development for the various designs. • Assistance in design based solutions to timing problems. • Coordination with team members in four locations across the globe. -
Senior Circuit Design EngineerIntel Corporation Jun 2016 - Jun 2017Santa Clara, California, UsStandard cell design, structured datapath design, timing methodology (processor and SoC):• Monte Carlo statistical simulations for POCV (parametric on-chip variation) coefficient modeling and methodology for Nanotime timing analysis. *• Scripting to automate the POCV simulations and data generation for new process corners and future technology changes.• SoC and processor core source-synchronous interface (timing across different clock domains, level shifting, and physical FIFO planning).• Balanced level shifter design to minimize duty cycle variation for clock transmission.• Specialized glitch gating standard cells for power reduction.• Structured datapath (SDP) FIFO design with Innovus.* AOCV, as the name suggests, was an advanced attempt to reduce pessimism in timing analysis by derating delays. This allowed for the accounting of multi-stage cancellations in delay variation. POCV builds on this effort by allowing the design team to run statistical simulations to generate variation coefficients (parameters) that are gate type and transistor threshold specific. POCV eliminates the need for stages, path type and corner delay to find delay derate data for timing analysis and characterization. -
Senior Circuit Design EngineerSoft Machines Feb 2014 - Jun 2016Santa Clara, Ca, UsCustom circuit design, memory & register file design, clock and noise methodology:• Advanced register file and multi-ported bitcell design for VISC processor architecture. *• Self-timed and frequency dependent margin analysis using Nanotime and Ultrasim.• Local clock distribution study and clock gating methodology.• Storage element design, including time borrowing flip-flops.• Robust noise methodology for dynamic circuit style read bitlines, overcoming Nanotime noise analysis limitations. • Keeper sizing study and guidelines.• Schematic entry & simulation (Hspice/Spectre/Ultrasim) standards and automation.* VISC processor architecture uses virtual cores and virtual threads as part of PPA (power/performance/area) optimization in the micro-architecture itself. -
Senior Memory Design EngineerNvidia Mar 2009 - Dec 2013Santa Clara, Ca, UsMemory design for high performance & low power ARM processor IP:• Full swing (8T bitcell) memory design concept evaluation.• Full swing level one data cache design (128kb banks for tag and data).• Full swing special purpose RAM design.• Heavy design reuse and common building block development for all 8T bitcell RAMs. • Assistance with NOR type CAM topology evaluation.• Design with low power in mind, power dissipation analysis and tradeoffs.• Extensive timing margin analysis using Nanotime and vector simulation using Ultrasim.• EM and IR drop analysis using the Ansys Totem tool.• Assistance in noise flow development using Nanotime.• Worked on Linux. -
Sram Design EngineerSun Microsystems May 2000 - Feb 2009Palo Alto, Ca, UsSRAM memories (6T & 8T), multi-cycle signaling, noise methodology for SPARC processors:• 6T differential and 8T full swing style RAM and CAM design. • Self-timed and frequency dependent timing margin analysis using the fast simulator XA.• Extensive work in the area of latch based multi-cycle signaling. • Simulation based time borrowing and timing optimization.• Inter-unit physical route planning with the integration team.• Redundancy methodology, dynamic design methodology, and noise methodology. • Worked closely with CAD developers on a project specific noise flow. • Lead junior engineers in an effort to obtain noise limit data for a multi-process environment.• Wrote project specific noise flow documentation. • Assisted the design team with the tools as well as solutions to noise problems. • Assisted CAD engineers in developing power analysis and Spice simulation scripts.• Worked on Solaris. -
Ip Design EngineerAtmos Corporation Aug 1998 - Mar 1999Redesigned IP library cells for compiler generated RAM, based on customer needs:• This semiconductor company created high density embedded DRAM cores for applications in the networking, wireless, graphics and imaging industries.• Worked on AIX.
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Design EngineerSgi Apr 1996 - Jul 1998Milpitas, Ca, UsCustom circuit design and verification on memory sub-blocks for MIPS processors: *• SGI was a computer systems company that optimized the MIPS architecture for graphics: processors such as R4k, R8k, R10k. • Most of Jurassic Park was done on SGI systems and the R4k processor powered the first Nintendo64.• Worked on IRIX.* Note: MIPS here comes from the micro-architecture term "Microprocessor without Interlocked Pipeline Stages" – e.i. simpler hardware, more advanced compiler. This is in contrast to other RISC processors that handle instruction dependencies in hardware – an example would be the SPARC "register windows".
Marek Smoszna Skills
Marek Smoszna Education Details
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Stanford UniversityVlsi Circuit Design -
Princeton UniversityNeuroscience
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University Of California, BerkeleyLeadership And Management
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De Anza CollegeComputer Programming
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Rensselaer Polytechnic InstituteElectrical And Computer And Systems Engineering
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Agh University Of KrakowElectrical And Electronics Engineering
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University Of SussexElectrical And Electronics Engineering
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Rensselaer Polytechnic InstituteElectrical And Computer And Systems Engineering
Frequently Asked Questions about Marek Smoszna
What company does Marek Smoszna work for?
Marek Smoszna works for Aril Inc.
What is Marek Smoszna's role at the current company?
Marek Smoszna's current role is Senior Staff Design Engineer.
What is Marek Smoszna's email address?
Marek Smoszna's email address is ma****@****ail.com
What schools did Marek Smoszna attend?
Marek Smoszna attended Stanford University, Princeton University, University Of California, Berkeley, De Anza College, Rensselaer Polytechnic Institute, Agh University Of Krakow, University Of Sussex, Rensselaer Polytechnic Institute.
What are some of Marek Smoszna's interests?
Marek Smoszna has interest in Science And Technology, Children, Education, Health.
What skills is Marek Smoszna known for?
Marek Smoszna has skills like Ic, Semiconductors, Vlsi, Cmos, Microprocessors, Processors, Soc, Very Large Scale Integration, Physical Design, System On A Chip, Static Timing Analysis, Eda.
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