Mario Bolanos Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

Responsible for strategic direction and operational efficiency of Intel PSG BU regional applications engineers around the world with offices in USA (San Jose, Austin, Chelmsford), Asia Pacific (Shanghai, Chengdu, Xian, Beijing, Shenzhen), Europe (UK – High Wycombe), Japan (Tokyo), Malaysia (Penang) My organization supports worldwide design win efforts together with field applications engineering, directly manage issue resolution related with our products and software, develop reference and example designs, provide training to customers, field applications engineers and distributors, support new product introduction.Manage Intel PSG Business Unit “War board”, which is the highest level executive escalation for complex issues that require executive management decision for resources and priorities allocation Member of Intel PSG Business Unit Quality Office My organization includes the Global Support Center that provides issue resolution for all worldwide broadbase customers, including design and debugging support of new products, responding to >10,000 customer service requests annually, and generating hundreds of collateral and reference designs for all new products

Responsible for strategic direction and operational efficiency of ~90 applications engineers.Managing Global Support Center for all international customers, including design and debugging support of new products, responding to >10,000 customer service requests annually, and generating hundreds of pieces of collateral and reference designs for all new products.Manage site level external engagement strategic initiatives, including government agencies, university relationships, R&D consortium and community related activities.Leader of Corporate Crisis Management Team representing Altera Penang

Dallas, Tx, Us

Test and Post Test Engineering Director at TI Malaysia supporting more than US$ 1 billion revenue per year, 400+ engineers and technicians. Responsibilities include equipment engineering, strategic business entity product engineering, process engineering, and Analog Engineering Organization Product Engineering, 24/7 hours/days/week operation.

Dallas, Tx, Us

Responsible for researching new, path finding and innovative assembly and packaging technology for Texas Instruments (TI) pace-setting semiconductor products. Develop research roadmaps, business case studies and strategic marketing plans to support new product Research and Development (R&D) opportunities. Manage TI’s strategic packaging research project portfolio and University collaborations. TI’s representative in several industry consortiums such as ITRS and iNEMI. Chair Person of Georgia Tech University EMAP consortium Industry Advisory Board and sits in the Statue University New York (SUNY) Binghamton IEEC and CAMM consortiums Industry Advisory Boards. Additionally I manage the TI’s Woman’s Fellowship at the Georgia Tech ECE. Medical Electronics Packaging Technology research and development roadmap definition and execution

Dallas, Tx, Us

Functional responsibilities included management of strategic research activities, Major focus was to select and develop from multiple technology alternatives, those that have the largest potential to turn into new products and generate revenue growth and competitive advantage for TI.• Successfully managed the development of several novel technologies from research to development, including next generation 3D miniaturized packaging solutions.• Managed worldwide university and research consortium activitiesDeveloped and implemented several world class technologies with multi billion dollar revenue and profit impact over several years time frame. All of them had major impact on the industry.  Enabled growth of the cellular phone market: The most successful Chip Scale Package (CSP) in the industry - u*BGA™ Improved profitability and enabled cost reduction in advanced semiconductor chips: New interconnection processes that allow wire bonding on top of active circuitry Enabled high performance products used in servers and telecommunications: Several generations of flip chip packages, from ultra high performance to low cost alternatives. Environmental impact: TI’s lead-free and ‘green’ packaging solutions Major cost reduction initiative: Cu wire bond to replace Au wire bonding Enabled further growth of potable electronics and consumer electronics: Next generation 3D miniaturized packaging solutions

Responsible for Equipment Engineering organization in TI Malaysia. His organization supports several thousand semiconductor devices automated production tools that produce several billions units per year. Additional this organization is focused on step function tool improvement, implementation of advanced maintenance systems, equipment utilization optimization, equipment upgrades, productivity improvements and major cost reduction programs

Mba, Executive Mba

Bachelor'S Degree In Business Adminstration, Business Adminstration And Management

Bsee, Electrical And Electronics Engineering

Education record

Bachelors Of Science Electrical Engineering, Electrical Engineering