Mario Bolanos

Mario Bolanos Email and Phone Number

Senior Director, Worldwide Regional Applications Engineering at Intel Corporation. Latino Corporate Directors Association (LCDA), HITEC100, SHPE Star Award, McKinsey Executive Leadership, Hudson Institute Licensed Coach @ Intel Corporation
(408) 765-8080
Mario Bolanos's Location
San Jose, California, United States, United States
About Mario Bolanos

GOALSA Vice President and General Manager role in the high tech industry where I can use my technical background (EE), business expertise (EMBA), leadership skills, and global work experience to increase profitability and shareholder value.SUMMARYPurposeful executive with distinguished record leading worldwide high-performance organizations, with multi-billion $’s business impact, setting and influencing global strategic direction, achieving substantial improvements, operational efficiencies and ability to perform across a global footprint. High technology industry expert with broad range leadership expertise, including R&D, Business Unit management, strategic vendor management, global manufacturing and technology operations, including a wide range of engineering and operations management roles. Functional strengths and experience built upon successful management positions in USA, Asia, and Latin America. 10 years as Corporate Packaging R&D Director at Texas Instruments (TI), executive sponsor of advanced material and equipment supplier’s strategic sourcing and management team and 20 years of Operations and Engineering leadership at TI in four different sites. 10 years applications engineering leadership at Intel Programmable Solutions (PSG) Business Unit, setting customer advocacy strategy, driving execution of operational strategies to increase business value to Intel, bringing the voice of customer to influence new product and features.World Class Industry Level Accomplishments in multiple areas:o Strategic vendor managemento Customer experience and business enablemento Global Leader expert o Integrated circuits electrical test operation and product engineering, o Corporate research and developmento New packaging technology.o Advanced semiconductor devices mega factory and operations management. AWARDS, PUBLICATIONS, AND TALENT DEVELOPMENTIEEE Senior Member, CPMT memberKeynote speaker at international conferences.Co-author of chapter in Power Integrity Analysis for Integrated Circuits book.Awarded 10 U.S. patents.Winner twice of the prestigious “Ideas in Action” Award given by TI’s CEOAwarded 8 times as One of the Most Influential Hispanics in Technology.Awards from SHPE, HENAAC, the New York State South Region Coalition.Contributed to Malaysia's Internet of Things (IoT) blueprint.Great recruiter and developer of key talent, e.g., five TI Fellows.EDUCATIONEMBA, University of Texas at Dallas – Valedictorian, GPA 4.0BSMA, BSEE, Universidad Centro Americana (Jesuit University)Fluent in English and Spanish

Mario Bolanos's Current Company Details
Intel Corporation

Intel Corporation

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Senior Director, Worldwide Regional Applications Engineering at Intel Corporation. Latino Corporate Directors Association (LCDA), HITEC100, SHPE Star Award, McKinsey Executive Leadership, Hudson Institute Licensed Coach
(408) 765-8080
Website:
intel.com
Employees:
10
Mario Bolanos Work Experience Details
  • Intel Corporation
    Senior Director, Worldwide Regional Applications Engineering
    Intel Corporation Mar 2018 - Present
    Santa Clara, California, Us
  • Intel Corporation
    Director, Worldwide Regional Applications Engineering
    Intel Corporation Feb 2016 - Present
    Santa Clara, California, Us
    Responsible for strategic direction and operational efficiency of Intel PSG BU regional applications engineers around the world with offices in USA (San Jose, Austin, Chelmsford), Asia Pacific (Shanghai, Chengdu, Xian, Beijing, Shenzhen), Europe (UK – High Wycombe), Japan (Tokyo), Malaysia (Penang) My organization supports worldwide design win efforts together with field applications engineering, directly manage issue resolution related with our products and software, develop reference and example designs, provide training to customers, field applications engineers and distributors, support new product introduction.Manage Intel PSG Business Unit “War board”, which is the highest level executive escalation for complex issues that require executive management decision for resources and priorities allocation Member of Intel PSG Business Unit Quality Office My organization includes the Global Support Center that provides issue resolution for all worldwide broadbase customers, including design and debugging support of new products, responding to >10,000 customer service requests annually, and generating hundreds of collateral and reference designs for all new products
  • Altera Corporation
    Director, Applications Engineering
    Altera Corporation Jul 2014 - Jan 2016
    Responsible for strategic direction and operational efficiency of ~90 applications engineers.Managing Global Support Center for all international customers, including design and debugging support of new products, responding to >10,000 customer service requests annually, and generating hundreds of pieces of collateral and reference designs for all new products.Manage site level external engagement strategic initiatives, including government agencies, university relationships, R&D consortium and community related activities.Leader of Corporate Crisis Management Team representing Altera Penang
  • Texas Instruments
    Director, Test And Post Test Engineering
    Texas Instruments May 2010 - May 2014
    Dallas, Tx, Us
    Test and Post Test Engineering Director at TI Malaysia supporting more than US$ 1 billion revenue per year, 400+ engineers and technicians. Responsibilities include equipment engineering, strategic business entity product engineering, process engineering, and Analog Engineering Organization Product Engineering, 24/7 hours/days/week operation.
  • Texas Instruments
    Strategic Research And University Collaboration
    Texas Instruments Feb 2009 - Feb 2011
    Dallas, Tx, Us
    Responsible for researching new, path finding and innovative assembly and packaging technology for Texas Instruments (TI) pace-setting semiconductor products. Develop research roadmaps, business case studies and strategic marketing plans to support new product Research and Development (R&D) opportunities. Manage TI’s strategic packaging research project portfolio and University collaborations. TI’s representative in several industry consortiums such as ITRS and iNEMI. Chair Person of Georgia Tech University EMAP consortium Industry Advisory Board and sits in the Statue University New York (SUNY) Binghamton IEEC and CAMM consortiums Industry Advisory Boards. Additionally I manage the TI’s Woman’s Fellowship at the Georgia Tech ECE. Medical Electronics Packaging Technology research and development roadmap definition and execution
  • Texas Instruments
    Research And Development Director, Semiconductor Packaging Technology
    Texas Instruments 1996 - Jan 2009
    Dallas, Tx, Us
    Functional responsibilities included management of strategic research activities, Major focus was to select and develop from multiple technology alternatives, those that have the largest potential to turn into new products and generate revenue growth and competitive advantage for TI.• Successfully managed the development of several novel technologies from research to development, including next generation 3D miniaturized packaging solutions.• Managed worldwide university and research consortium activitiesDeveloped and implemented several world class technologies with multi billion dollar revenue and profit impact over several years time frame. All of them had major impact on the industry.  Enabled growth of the cellular phone market: The most successful Chip Scale Package (CSP) in the industry - u*BGA™ Improved profitability and enabled cost reduction in advanced semiconductor chips: New interconnection processes that allow wire bonding on top of active circuitry Enabled high performance products used in servers and telecommunications: Several generations of flip chip packages, from ultra high performance to low cost alternatives. Environmental impact: TI’s lead-free and ‘green’ packaging solutions Major cost reduction initiative: Cu wire bond to replace Au wire bonding Enabled further growth of potable electronics and consumer electronics: Next generation 3D miniaturized packaging solutions
  • Texas Instruments Malaysia
    Director, Equipment Engineering
    Texas Instruments Malaysia May 2010 - Nov 2011
    Responsible for Equipment Engineering organization in TI Malaysia. His organization supports several thousand semiconductor devices automated production tools that produce several billions units per year. Additional this organization is focused on step function tool improvement, implementation of advanced maintenance systems, equipment utilization optimization, equipment upgrades, productivity improvements and major cost reduction programs

Mario Bolanos Skills

Semiconductors Electronics Ic Process Engineering Product Engineering Semiconductor Industry Manufacturing Analog Product Development Engineering Management Cross Functional Team Leadership Asic R&d Mixed Signal Failure Analysis Cmos Testing Engineering Microelectronics Process Integration Silicon Test Engineering Operations Management Pcb Design Analog Circuit Design Technology Transfer Electrical Engineering Design Of Experiments Process Improvement Mems Dft Vlsi Integrated Circuit Design Assembly Cost Reduction Process Development Yield Power Management Digital Signal Processors Semiconductor Manufacturing Technology Development Yield Enhancement Soc Supply Chain Management Thin Films Rf Hardware Architecture Process Simulation Eda Simulations

Mario Bolanos Education Details

  • The University Of Texas At Dallas
    The University Of Texas At Dallas
    Executive Mba
  • Jesuit College (Universidad Centro Americana Jose Simeon Canas)
    Jesuit College (Universidad Centro Americana Jose Simeon Canas)
    Business Adminstration And Management
  • Jesuit College (Universidad Centro Americana Jose Simeon Canas)
    Jesuit College (Universidad Centro Americana Jose Simeon Canas)
    Electrical And Electronics Engineering
  • Liceo Salvadoreno
    Liceo Salvadoreno
  • Universidad Centro Americana
    Universidad Centro Americana
    Electrical Engineering

Frequently Asked Questions about Mario Bolanos

What company does Mario Bolanos work for?

Mario Bolanos works for Intel Corporation

What is Mario Bolanos's role at the current company?

Mario Bolanos's current role is Senior Director, Worldwide Regional Applications Engineering at Intel Corporation. Latino Corporate Directors Association (LCDA), HITEC100, SHPE Star Award, McKinsey Executive Leadership, Hudson Institute Licensed Coach.

What is Mario Bolanos's email address?

Mario Bolanos's email address is mb****@****aol.com

What is Mario Bolanos's direct phone number?

Mario Bolanos's direct phone number is +146944*****

What schools did Mario Bolanos attend?

Mario Bolanos attended The University Of Texas At Dallas, Jesuit College (Universidad Centro Americana Jose Simeon Canas), Jesuit College (Universidad Centro Americana Jose Simeon Canas), Liceo Salvadoreno, Universidad Centro Americana.

What are some of Mario Bolanos's interests?

Mario Bolanos has interest in Children, Education.

What skills is Mario Bolanos known for?

Mario Bolanos has skills like Semiconductors, Electronics, Ic, Process Engineering, Product Engineering, Semiconductor Industry, Manufacturing, Analog, Product Development, Engineering Management, Cross Functional Team Leadership, Asic.

Who are Mario Bolanos's colleagues?

Mario Bolanos's colleagues are Si Woo Park, Robert Gilchrist, Ramya Nair, Bree Drda, Sejal Mehta, Praveen Raj, Brian Huffman.

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