Mark C. Email & Phone Number

台灣

台灣 新竹縣市

One of the major founders of Algoltek, Inc.Develop the execution strategy to achieve engineering and business team roadmap requirements.ASIC flow and design methodology defining and building.Responsible for following products: HDM2VGA converter, MHL2HDMI converter, Power Delivery controller, Wireless Charging (Qi) and USB 3.0 PHY.

竹北市

Responsible for design architecture design, team coordinating and IP promotion. The USB 3.0 PHY sample chip has been released on 2010 with UMC 110nm process.

台灣 台北市

*Wireless communication Business Unit 2006/09 ~ 2008/09Built a new design team to develop an Ultra-Wide Band (Wireless USB) SOC. The IC includes a 16bit MCU, WUSB MAC protocol engine, AES128 and IDE controller. Responsibilities include chip architecting, RTL coding, firmware interface definition, FPGA prototyping, ASIC process, project supervising and junior engineer educating.*IO product line hardware team leader 2004/02 ~ 2006/08Design tasks: Lead the IC design team to develop USB 2.0 card reader, USB flash controller, MP3 player, USB hub and Key board products. Responsible for FPGA/ASIC design methodology definition, projects supervising, schedule managing, top-level integration, ECO and timing closure.Mass production tasks: Responsible for mass production affairs, which include functional pattern qualification, testing/packaging issue solving and customer feedback trouble shooting. The major product, card reader product line, has multi-million pieces volume per month.EDA tools management: Internal CAD tool supporting, management and surveying.

Santa Clara, California Usa

*SAN/IP Switch fabric micro architecture design and implementation: Participated a high performance network switch fabric chipset development. Both chips contain multimillion gates and run at 250Mhz and 150Mhz.*Physical synthesis and timing flow development: Developed physical synthesis (Cadence PKS) flow scripts and constraints by TCL/C-shell languages. Worked on the floor plan, clock tree distribution and timing closure.*Static Timing Analysis: Responsible for whole chip static timing analysis.

San Jose, California Usa

*Memory BIST & DFT: Responsible for DFT implementation which includes MBIST, Scan insertion, IO level testing, JTAG and ATPG generation*System On Chip Design: Joined the development of embedded system products. Responsible for peripheral IP integration with ARM920t via AHB.*Design Service: Responsible for being the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers.

San Jose, California Usa

*Embedded System Design: Successfully designed a SOC product. Design includes Hitachi H8S microprocessor, CAN (controller area network) and other peripheral IPs. Responsibilities include RTL DFT, ATPG, functional verification and P&R.*IP supporting: Provide direct customer support for foundation IP (standard cell, I/O, memory, PLL and analog cells).*Design Service: Responsible for ASIC constraint validation, floor planning, timing analysis, package issues and power management.