Mark Condit Email & Phone Number

Designed, built and used a SystemVerilog OVM based Test bench for the Teradyne Timing Generator Program. Timing Generator is a cutting edge time and signal measurement ASIC design. Intended for Teradyne's advanced high speed chip testing applications. The test bench provides reference models that predict time and signal measurement results based on input.

Lead team in the verification of 5 mixed signal ASICs, intended for high accuracy temperature measurement in personal computers. These ASICs, employ a "Sigma Delta" analog front end and a discrete DSP digital back end. The VMM type SystemVerilog test bench modeled the Sigma Deltas output as a function of temperature and then predicted the results of the.

Coded and simulated "Perl generated" random Verilog System Level Test suites for Pre-silicon RTL. This INTEL ASIC was an SOC based on the ARM9 processor intended for the cell phone market. Our tests where intended to verify the operation of the numerous peripherals and their interaction with each other and with the processor. These interactions occurred.

Designed and verified Sub Modules for three SOC ASICs. For two SOCs I designed and verified an I2C Interface circuit. For another SOC I Designed and verified a 133MHZ Triple DES engine for data encryption. I also ran Formal Verification for a 500k gate ASIC and updated scan test for IC already in production

Lead team through the design and production of L Band Satellite modem. Designed EuroCom Interface FPGA for.

Designed Digital controller for Military Laser Designator. Lead Prototype build and test. Supported Unit Integration in follow on contract with Litton Laser

Responsible For design and support of Analog and Digital CCAs for Military and Commercial Avionics. Focused on Cockpit displays, AutoPilots and Flight Management Computers.