I am an FPGA Design Verification engineer with multiple years of experience leading multi-FPGA DV efforts, utilizing primarily UVM and SystemVerilog in mixed language environments that include Verilog, VHDL, Matlab and C++ components. Responsibilities include; writing Test Plans with requirement mapping and coverage closure in mind, developing UVCs and Scoreboards for pseudo-random stimulus and self-checking, and assisting in developing solutions to uncovered design flaws. I personally find great pleasure in identifying bugs and working with the design team to resolve them, and ultimately bringing the design to a successful closure. While I spend most of my time in the Questa Simulation Environment, I have never been afraid to pull up my sleeves and assist in debugging in the lab.