MPS is a Minnetonka Minnesota based start-up working on reinventing the parking industry by deploying high tech solutions that leverage state-of-the-art cloud, M2M, applications, video, and messaging.

Executive level engineering position. Chief Engineer on new flash memory (Solid State Disk) optimized storage products and next generation chip based solutions. Responsible for design, technical oversight of 50+ engineers and product delivery working across functional organizations (software, chip logic design, test, procurement, and card design) to define development plans and drive plan execution. Quickly developed strategic relationships across the company worldwide to deliver objectives. Stayed hands on with design and implemented new cache design with patent disclosures. Delivered ResultsDrove all components of project (FPGA logic design and verification, firmware, cards and test) to delivery.Resolve architectural issues to allow deployment in large enterprise class storage solutions.Increased efficiency and quality by improving numerous development processes.Modernized test methodology to deploy and leverage test automation.

Complete rebuild of engineering organization into a high energy and highly motivated team. Complete refresh of product lines for RAID software and adapter business for Windows, Linux and Mac OS, Direct Attached Storage appliances, Network Attached Storage appliances and rugged military grade storage appliance business. Involved in numerous pieces of the business; operations, sales, support, and marketing. Responsible for all product details and major technical decisions. Direct report to CEO. Delivered ResultsRebuilt engineering team from 2 to 26 software, hardware and test engineers.Produced multiple, reliable, product releases with high level of schedule integrityRebuilt development process based on ISO 9002 and passed inspection.Implemented state of the art, integrated configuration management, build and test automation system.Successfully integrated development team with large (Patni) and small (MSys) off shore resources.

Designed and implemented Linux kernel drivers to provide interfaces to IBM Axon south bridge. Designed and developed multiple models of Axon components to allow the rapid development of drivers and chip verification software.

Led and participated in the product development lifecycle for storage over IP solutions: UltraNet Storage Director (USD), UltraNet Edge Storage Router (now sold by Brocade) and UMD WAN blade products from initial design through development and testing to initial shipment, generating more than $1B in revenue. Led a team of more than 20 engineers and built strong internal and external vendor relationships to ensure resource availability. Direct report to VP of Engineering/CTO. Delivered ResultsDesigned and implemented Linux kernel drivers to: Fibre Channel controller FPGA, SerDes, and optical interfaces; support board-level events, such as power, temperature, bus errors, and parity; and develop Mid-plane and Arbiter adapters, WAN adapter cards, compression subsystems, TCP network processors, Gigabit Ethernet MAC, Ethernet PHYs, optical interfaces, and internal data path switch FPGAs.Created and deployed I2C sensor network on-board and API for System Health Monitor daemon. Revamped Monta Vista Linux, enhancing board-specific architecture, including DMA scatter/gather driver, I2C, memory controller, RTC, and panic-processing capabilities. Created the system software architectures for the UltraNet Edge and UMD WAN blade. Led the creation of a key technology that facilitated the smooth and secure block storage data migration across long distance networks.Co-created the Fibre Channel controller FPGA architecture. Served as point-of-contact for all quality assurance (QA) issues and contributed to the development of the QA automated regression suite design.

Designed an innovative system software architecture for the UltraNet Edge Storage Router, including porting Nucleus RTOS to PowerPC 750 in addition to implementing improvements in interrupt context handling, interrupt control, and system clock timing. Secured a software patent related to Fibre Channel frame batching. Created various diagnostic tests to evaluate system runtimes and identify hardware FPGA logical errors in multi-ported data path memory; developed and deployed a DMA subsystem to interface with FPGA logic, facilitating high speed buffering of Fibre Channel frames. Served as point-of-contact for all quality assurance and customer conflicts. Utilized an IBM PPC750 processor running the Nucleus-embedded operating system for project development. Mitigated more than 300 reported quality assurance defects during alpha and beta testing, ensuring product reliability.Delivered Results Developed boot firmware, facilitating initial board powering. Created and deployed a 10/100 multi-port Ethernet driver as well as a Gigabit Ethernet driver.

Environment: Solaris, Nucleus, UNIX, C, C++, POSIX threads, SingleStep (for pROBE ); Managed the design and development of a completely new architecture. Utilized a Sun SPARC running Solaris and an IBM PPC603e processing running the Nucleus-embedded operating system for development projects.Delivered ResultsCo-designed a Switch Interface Controller (SIC) FPGA, which controls the non-blocking switch backplane allowing SPARC-based Service Monitor cards, PowerPC based I/O cards, and M68020 ESCON cards to communicate in the director chassis. Created the Solaris kernel driver and the Nucleus driver and API's for SIC. Deployed an Ethernet driver for PowerPC-based boards boot firmware. Designed and developed the DEC 21041 Ethernet controller driver for Nucleus.

Environment: C/C++, Solaris, UNIX, SPARC, HIPPI, IPI-3, VM.; Designed and implemented a multi-dimensional swapping system. Contributed to the development of an intelligent I/O channel controller and created a related software simulation. Coordinated with IBM San Jose, the builders of the supercomputer's disk subsystems, to ensure efficient design and development.Developed and integrated kernel code for disk I/O systems on the AT&T System V.4 UNIX-based port-to

Environment: C/C, system/370 assembly, UNIX, AIX, VM, MVS.; Contributed to a joint venture that developed a multi-processor version of AIX running on 3090 vector mainframes. Evaluated on-site data to identify and mitigate kernel inefficiencies and liaised between the customer and remote IBM development organizations to achieve project needs and facilitate smooth development. Communicated with customers to gather requirements and troubleshoot problems.

Environment: C/C, NOS, NOS/VE, TCP/IP, CDCNet, FORTRAN; Provided NOS and NOS/VE operating system customer support as well as various programming services. Built a strong relationship with Briggs and Stratton, delivering the account from a potential loss to a satisfied, recurrent customer, generating multiple streams of revenue.