Mark Stephenson Email & Phone Number

Santa Clara, Ca, Us

I am a member of the Architecture Research Group at NVIDIA. I have focused primarily on compiler analyses and tools for both CUDA and graphics workloads.

Armonk, New York, Ny, Us

During my time with IBM my projects spanned a diverse range of topics, focused primarily on compilers and computer architecture. I have written a few important applications for large-scale systems. In particular, I wrote a high-performance, fault-resilient FFT library for the IBM PERCS system, and a Hadoop-based HTML parsing engine for a moderately sized IBM Power 7 cluster. Previous projects include the hardware/software co-design of a lightweight predication scheme, and language extensions and associated compiler and runtime system support for detecting anomalous program behavior.

Cambridge, Ma, Us

For my PhD and Masters I was primarily advised by Professor Saman Amarasinghe. I was the leader of a project that focused on using machine learning techniques to make sense of complicated computer systems. I worked closely with machine learning researchers and systems researchers to develop techniques to analyze and design modern-day systems. Our systems automatically extract empirical performance data from running applications, which they then use to automatically generate improved compiler and runtime optimizations. The project spanned several large compiler infrastructures including Trimaran, the Open Research Compiler, and the Jikes Research Virtual Machine. I directly supervised two Master's students.Earlier in my career at MIT, I was also advised by Professor Anant Agarwal. Under Anant, I assisted in the early design and study of the RAW architecture project. In particular, I helped design the floating point ALU and the data cache. For my Master's thesis I developed a compiler analysis in SUIF that statically determines the minimum number of bits needed to represent an input program's variables. We successfully applied our system to hardware synthesis from the C programming language.

Advised by Professor Al Davis and Professor Erik Brunvand. I was a member of the Avalanche Project which sought to create an inexpensive multiprocessing system by designing a bus card that tightly couples a machines's processor and memory system to a fast network fabric. I wrote a VHDL description for the test chip's two-way set associative data cache. In addition I performedVLSI layout for a number of the test chip's components.

Washington, Dc, Us

Doctor Of Philosophy (Phd), Computer Science

Bachelor'S Degree, Computer Engineering