Mark Yu Email & Phone Number

2010-2022CSP customer server product enabling.● Manage multiple development projects based on established priorities● Work with the cross-functional group to provide proposals to customers based on requirements (1U, 2U, 4U). It includes mechanical, signal integrity (pre-simulation), hardware design, thermal simulation, cost evaluation.● Communicate with the customer to define hardware topology requirement and design study.● Perform schematic design review and work with CAD team on PCB layout to ensure good signal integrity for mix-signal boards.● Review signal integrity, power integrity simulation, and DFx at the design stage.● Responsible for hardware bring-up and troubleshooting.● Develop and implement and execute test plans. Review hardware validation report, system integration test.● Work with cross-functional groups to resolve functional bugs.● Manage the BOM and survey 2nd source to reduce shorage impact.● Factory brings up and manufacturing test support.● Perform manufacture test reviews and work with the cross-functional group to help to improve the first pass yield.Project design working history base on Platform design and timeline list.● AMD G34 2010-2011● Intel Romley platform 2011-2012● AMD Bulldozer AM3 2012● IBM POWER8 2013-2014 ● Intel Broadwell-DE 2015-2016 ● Intel Purley platform 2016-2017● AMD EPYC SP3 Naples/Rome 2017-2019● Intel Whitley platform 2019-2020● AMD EPYC SP5 Genoa 2020-20212022-Now● Ampere CPU Senior platform application engineer (ODM Enabling)