Mark Fuselier Email & Phone Number

Santa Clara, California, Us

- Lead Global Engineering team responsible for the definition, development and production ramp of AMD's technologies and products - Define and develop AMD's high performance processor products, including product test and diagnostics through high volume manufacturing and customer support alongside AMD business units - Develop industry leading technologies in both silicon process and advanced packaging alongside manufacturing partners

Santa Clara, California, Us

- Lead global team responsible for development of new products and technologies to achieve target performance, power, and cost to drive AMD's roadmap. - Define and execute AMD's foundry process technology roadmap, including execution on current production through definition of 3-5 year technology roadmap. - Execute AMD's manufacturing development and qualification process across all products, including product definition, testpoint definition, test program release, and qualification of production recipe.- Achieve AMD's product targets for yield, cost, quality, performance, power based on characterization of early ASIC silicon, optimization of product and test configuration and specs.- Define and execute AMD's test hardware and test methodology roadmap, including test methodology, test specs, test board and tester configuration. - Define and execute AMD's data systems and tools used to drive product yield and manufacturing optimization.

Santa Clara, California, Us

- Lead AMD's Foundry Technology and Global Supplier management teams. Define, select, and manage AMDs foundry technology; select and manage all AMD direct and indirect materials spend ($3B annual spend); manage global business procurement spend at AMD;

Santa Clara, California, Us

- Define, select and manage AMDs foundry process technology working with a global foundry supply base; lead foundry procurement ($2B annual spend);

Santa Clara, California, Us

- Lead product and test engineering to support AMD's server, low power, and console product lines.

Santa Clara, California, Us

- Accountable for product definition, characterization, test development and manufacturing product engineering supporting server and client products across AMD's portfolio. - Drove introduction of multiple process technology nodes (130nm, 90nm, 65nm, 45nm, 32nm) through definition, planning, NPI and manufacturing phases

Armonk, New York, Ny, Us

- Defect and yield characterization on IBMs 0.35um bulk CMOS technology, and IBM's first SOI technology, at 0.25um.

Master Of Business Administration (Mba), Business Administration And Management, General

Ms Ee, Electronics / Semiconductor Physics

Bachelor'S Degree, Electrical And Electronics Engineering