Nov 2023 - Present
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Mark Bellows Email & Phone Number
System Validation/Verification Engineer Ready To Solve Your Vexing Hardware Problems
at
Idaho Scientific
1 work email found
@intel.com
1 phone found area 408
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
System Validation/Verification Engineer Ready To Solve Your Vexing Hardware Problems
Location
Salt Lake City, Utah, United States
Who is Mark Bellows? Overview
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Quick answer
Mark Bellows is listed as System Validation/Verification Engineer Ready To Solve Your Vexing Hardware Problems at Idaho Scientific, based in Salt Lake City, Utah, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 408, and a matched LinkedIn profile for Mark Bellows.
Mark Bellows previously worked as Verification Engineer at Idaho Scientific and Seeking opportunities to solve your problems and mentor your people at Validation And Verification Engineer. Mark Bellows holds Master Of Science (Ms), Electrical And Electronics Engineering from University Of Minnesota-Rochester.
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{first}.{last}@intel.com
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Profile bio
About Mark Bellows
RESULTS-DRIVEN COMPUTER HARDWARE ENGINEER FOR INCREASING QUALITY AND MENTORINGWiling to relocate, I'm an Computer Engineering Professional seeking a job in the technology field. I've been in the field for more than 20 years and have worked from the layout of transistors to putting together systems. I've spent time in the verification of logic, to writing logic, to testing logic. I am proficient in C++, python and Perl too. I enjoy mentoring junior engineers so that they can be as proficient as I am.Expertise in:• Issue Resolution • Developing / Implementing Test Cases• Cross-Functional Team Leadership • Hardware Optimization• System Verification • Training / MentoringTECHNICAL SKILLSLanguages: C, C++, perl, python, VHDL, Verilog, SystemVerilog, UVM, perspec, C/Bash shellPlatforms: Unix, Linux, FPGAApplications: ModelSim, MS Office Products, CadenceOther: Team Leader, Trainer, Mentor, Logic and Software Debug, Verification, Validation, Simulation, Design, PCI interface, LP/3/4 DDR3/4/5, XDR, Firmware, Hardware bring up, lab, Synthetic ContentRecent Course WorkMastering SystemVerilog UVM, Sutherland HDL, July 2014SystemVerilog Object Oriented Verification, Sutherland HDL, June 2014I like controlled processes and was a SCRUM Master in a roll out of Agile in a Hardware Validation role. Although there was a huge inertia to move people to this mindset, I found it as a great framework to manage the timely and controlled delivery of getting things done for the customer.Some of the experiences I have had in my computer hardware engineering career working on different products and systems:* driving failure escapes into improved testing* enhancing automation* figuring out hardware/software bugs* development and design methods* team work * read requirements and specifications * cutting edge technology* verification skills and making sure things are functional* test of hardware* measuring and improving performance* satisfying customers* responsible for memory firmware* integration of chips into systems* support my colleagues with tools* communication written and verbal* verification and debugging hardware* computer programming and making unique high quality solutions* computer architecture - digital design* innovation in writing software* integrating software* creating new functions for new features* pathfinding and evaluating different alternatives
Listed skills include Perl, Unix, C++, Firmware, and 20 others.
Current workplace
Mark Bellows's current company
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12 roles
Mark Bellows work experience
A career timeline built from the work history available for this profile.
Seeking Opportunities To Solve Your Problems And Mentor Your People
Validation And Verification Engineer
Oct 2023 - Nov 2023
Manager 2-Senior E/E & Semiconductor Engineer
Working with a client on computer vision - Pre-Silicon work preparing for post silicon. Completed Tensilica Xtensa LX Processor Fundamentals v9.6 course.
Apr 2023 - Oct 2023
System Validation Engineer
Sep 2019 - Apr 2023
System Validation Engineer -Experienced Ddr3/4 Post-Si Validation
Working in Development on Memory for different products + Using JEDEC standards to validate designs+ leading a team to validate hardware designs
Sep 2014 - Sep 2019
Experienced Electrical Engineer
Seeking New Opportunities
Looking for new opportunities in the Computer IndustryCourseworkSystemVerilog Object Oriented Verification, Sutherland HDL, June 2014
Apr 2014 - Sep 2014
Advisory Engineer
Ibm
Memory Interface to DDR3/DDR4 VBU and Lab ToolsMemory Subsystem Development for the pSeries/zSeries/iSeries/blade center IBM servers. Tasks involved bring-up and optimization of register settings. The team leader for the Virtual Bring Up (digital simulation of the complete computer system) for DDR3 and DDR4 Memory Subsystems. Also worked with Flash Memory.
Nov 2007 - Mar 2014
Staff Engineer
Ibm
Follow on Processor WorkFollow on processors called SStar and a variation of the SStar called Vervain. This second chip was a memory controller chip.Also during this time I worked on a PCI to RIO (and IBM high speed interface bus) converter chip called Speedwagon. This chip had 2 RIO buses and 3 PCI buses.Verification of IO Adapter Chip Lead the.
May 1998 - Nov 2007
Engineer
Ibm
Verification of IO Adapter ChipLead the verification of a low end memory and IO (PCI) adapter chip for the AS/400. First pass hardware worked without any bugs.
Dec 1996 - May 1998
Senior Associate Engineer
Ibm
Internal/External Cache (SDRAM) and Memory Interface Verification Verification of the processor cache controllers for the Pulsar and Northstar processors which were the power house for many of the IBM low to midrange systems during this time. This involved creatively linking up a testbench and random testing suite to drive out bugs in the cache, L2 cache.
Jun 1995 - Dec 1996
Associate Engineer
Ibm
Continuation of 64bit Floating Point VerificationMy most favorite bug found was in the rename logic. This stumped people, but I was able to determine the problem, provide a solution to get the product out the door.I also enjoyed finding and fixing bugs in the checker unit - a piece of logic that checks that the 64 bit floating point got the right answer.
Sep 1993 - Jun 1995
Engineer
Ibm
64bit Floating Point VerificationVerification of hardware for Floating point unit and processors for the AS/400. Random Testcase generation and verification of hardware.
Oct 1992 - Sep 1993
3 education records
Mark Bellows education
Master Of Science (Ms), Electrical And Electronics Engineering
University Of Minnesota-Rochester
Bachelor Of Science (Bs), Electrical And Electronics Engineering
Brigham Young University
Education record
Wasatch High School
FAQ
Frequently asked questions about Mark Bellows
Quick answers generated from the profile data available on this page.
What company does Mark Bellows work for?
Mark Bellows works for Idaho Scientific.
What is Mark Bellows's role at Idaho Scientific?
Mark Bellows is listed as System Validation/Verification Engineer Ready To Solve Your Vexing Hardware Problems at Idaho Scientific.
What is Mark Bellows's email address?
AeroLeads has found 1 work email signal at @intel.com for Mark Bellows at Idaho Scientific.
What is Mark Bellows's phone number?
AeroLeads has found 1 phone signal(s) with area code 408 for Mark Bellows at Idaho Scientific.
Where is Mark Bellows based?
Mark Bellows is based in Salt Lake City, Utah, United States while working with Idaho Scientific.
What companies has Mark Bellows worked for?
Mark Bellows has worked for Idaho Scientific, Validation And Verification Engineer, Capgemini Engineering, Intel Corporation, and Seeking New Opportunities.
How can I contact Mark Bellows?
You can use AeroLeads to view verified contact signals for Mark Bellows at Idaho Scientific, including work email, phone, and LinkedIn data when available.
What schools did Mark Bellows attend?
Mark Bellows holds Master Of Science (Ms), Electrical And Electronics Engineering from University Of Minnesota-Rochester.
What skills is Mark Bellows known for?
Mark Bellows is listed with skills including Perl, Unix, C++, Firmware, Debugging, C, Simulations, and Asic.
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