Mark Foltz Email & Phone Number

Pittsburgh, Pa, Us

Zurich, Zh, Ch

Turbine Control PRUProcess Automation / Power GenerationSenior Research and Development EngineerPromotion-In-Place

Zurich, Zh, Ch

Turbine ControlPower Systems / Power GenerationResearch and Development EngineerDesign and verify embedded features for existing Turbine Control Products - Firmware upgrades for legacy turbine protection and auto synchronization products (embedded C) - Debug and execute postmortem analysis on modules returned from the field - Analyze systemic and manufacturing quality issues - Debug communication interfaces including Profibus, Modbus, and proprietary interfaces - Support business units globally on turbine related projectsDesign and verify (schematic / layout / firmware) embedded features for next generation Turbine Control Products - Lead research and development initiatives for physical and logical interface architecture within next generation platform - Conduct feasibility studies on closed loop response time optimization - Power supply / hot swap / power sequencing circuits - Digital circuits (Coldfire CPUs, Spartan 6 FPGAs, CoolRunner-II CPLDs, DDR2) - Serial communication interfaces, including RS485, RS232, and USB - Analogs, including low and extra low voltage inputs; 4-20mA receivers / transmitters, phase / frequency detect circuits - 61010 compliance analysis - Board bring-up, boot code integration (C/Assembly) - Peripheral drivers (C/Assembly/VHDL) - RTOS application programming (C) - Optimize proprietary communciation interfaces to improve total system response time (C/VHDL)New Product Introduction - Create, review and release product manufacturing drawings (PTC Creo/ODB++/Excel) - Run meetings interfacing with contract manufactures to handle any technical or logistical issues on aggressive schedules - Design automated manufacturing test systems to improve hardware test coverage and reduce time to ship (C++/TCL/Expect/USB/GPIB/Ethernet)

Zurich, Zh, Ch

Turbine ControlPower Systems / Power GenerationResearch and Development Engineer (Additional Responsibilities)Development and Quality Management - Project planning and tracking using Microsoft Team Foundation Server - Run meetings interfacing with Software teams to set requirements and ensure new products are handled and easily configurable through HMI - Internal team auditing and training coordination to meet group quality initiatives - Meet with global quality group to discuss issues and road-map - Mentoring and training co-op student employeesGroup IT - Installation and maintenance of internal lab network with multiple subnets and VLANs - Installation and maintenance of license and tools servers - Installation and maintenance of developer build environments - Installation and maintenance of VM servers (ESXi) - Creation and deployment of VM's for development test systems

Plano, Tx, Us

Network Solutions R&D DivisionFPGA Logic Design and VerificationNPU Fastpath ImplementationOwned Egress Data Buffering FPGA for custom CESR chipsetMultiple clock domain, 160MHz, Multiple SerDes Interfaces, DDR2 Memory InterfacesImplemented HDL feature additions to support Y1731 TimestampingOptimized chip for fitting and timing closureGenerated debug images with custom logic for customer releases to analyze site-specific issuesSite Lead and trainer for high level verification environment setup using Specman eDeveloped Fastpath microcode for custom chipset and EZChip based designsC++ chip driver bug fixes and feature changesReduced risk of a $300K silicon respin by defining and performing tests on unreleased chipset features before tape outCollaborated with international R&D team members

Chandler, Arizona, Us

Primary developer on an internal design and test tool for the FPGA teamPresented ideas to improve productivity and reliability of the systemImplemented improvements and additions to the systemImprovements increased searchable record retention ability and reduced effort of the chip release processTrained other employees on proper use and maintenance of the systemImproved documentation and development methods to ease future development

St. Louis, Mo, Us

Primary developer on NPI Team project for industrial CPU power fault detection and backupStudied recently released NPI project that was to be improvedBenchmarked and evaluated parts from multiple manufacturers and discussed parts with technical sales repsImplemented switching power supplies including Buck and SEPIC topologiesIntegrated super capacitors after evaluating ESR and electrolytic characteristicsAssembly programmed Microchip PIC and TI MSP430 microcontrollers using MPLAB and IAR