Silicon Lifecycle Management Strategy • Product owner for software that feeds silicon test data into design tools • Product owner for sensor analyticsApplication Engineer for SiliconDash • Technical support, training and project management for US customers • Drove adoption of SiliconDash with new customers • Assisted sales and marketing in creating new documentation and presentations

• Oversee and execute high-volume semiconductor test data-integration projects. • Technical interfacing with customers. Provide application support and yield analysis services. • Work with customers, and internal development/product management teams to define product opportunities and establish technical strategies. • Pre-sales activities with the business development team to demonstrate Qualtera's solutions • Provide input for software development specifications to address advanced customer needs.

Silicon to PDK validation for 16nm to 5nm finfet technologies • Performance limited yield and power/performance optimization with machine learning algorithms. • Silicon characterization through test chip analysis. Identification of gaps to design PDK and forward feedback to improve the design yield and power/performance before tapeout. • On-site supplier support to rapidly identify and fix process yield issues. • Provide additional yield debug support for particularly challenging product yield issues. Root caused a failure mode on preproduction silicon that provided a yield boost and Vmin reduction for the production design. • Wrote yield analysis software. It’s unique design allows for rapid, repeatable interactive analysis. Features include batch processing on server farm and automated web reports.

Lead test chip yield engineer for 20nm and 16nm finfet processes:• Used statistical methods to determine which process characteristicspredict what type of failure mode. Highlighted process risk before production silicon.• Yield analysis highlighted product risks that directly lead to product roadmap changes.Test chip yield engineer for 32nm, 28nm and 20nm processes:• Analysis and debug of design and process yield signals has lead to faster bring-up of GPUs and accelerated product ramp of APUs.• Boundary scan, BIST, at-speed scan and HTOL analysis.Product yield engineer for Llano 32nm APU:• Led early bring-up yield enhancement efforts. • Debug of fabrication process, test programs and characterization analysis. Product yield engineer for Griffin 65nm laptop CPU:• Guided yield enhancements from the middle of the product ramp phase to sustaining mode. • Led efforts to transition yield analysis from bring-up team in Austin to sustaining team in Suzhou, China. • Yield loss debug and test optimization made Griffin the all-time highest yielding product.Other Responsibilities:• Written requirements for in-house analysis software tool. New features have made the yield team more productive and given the ability to do deeper analysis.• Created yield analysis training course. Given the course to teams in Austin, Toronto and Singapore. Measurable product yield increase after teams are trained.

Provided on­site design for manufacturability (DFM) and yield consulting for fabrication plants.• Identified process drifts and unintended consequences of process changes that led to corrective action and increased yields. • Created new software features and wrote comprehensive software specifications resulting in a patent submission. • Decreased creation time from 3 weeks to 4 hours by designing methodology to automate test vehicle design. • Reduced salary costs by 90% on design projects by training and managing a team of engineers in Armenia. • Managed projects and provided test structure designs for 45 and 32nm technology nodes.

Project manager for test chip deliverables and DFM engineer.• Drove an effort to automatically capture design data in a relational database, thereby allowing multi­site teams to work more effectively on projects. Led to a reduction in project cycle time by 33% which increased project margins from ­12% to +10%. • Managed projects and provided test structure designs for 90, 65 and 45nm technology nodes. • Responsible for new employee recruiting, hiring and training.

Provided test structure design for 180, 130 and 90nm technology nodes. • Completed test lab training, trained on the HP 4186 tester, Keithley switching matrix and automated prober. • Conducted trademark research and application submission to the US Patent and Trademark Office.