Mark Scheitrum
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Mark Scheitrum Email & Phone Number

Location: San Jose, California, United States 8 work roles 1 school
1 work email found @atessainc.com 5 phones found area 408, 619, and 925 LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email · 5 phones

Work email m****@atessainc.com
Direct phone (408) ***-****
LinkedIn Profile matched
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Current company
Role
COO
Location
San Jose, California, United States
Company size

Who is Mark Scheitrum? Overview

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Quick answer

Mark Scheitrum is listed as COO at Atessa, Inc., a company with 9 employees, based in San Jose, California, United States. AeroLeads shows a work email signal at atessainc.com, phone signal with area code 408, 619, 925, and a matched LinkedIn profile for Mark Scheitrum.

Mark Scheitrum previously worked as Vice President Engineering at Cpu Tech and Vice President Systems Engineering at Chameleon Systems, Inc. Mark Scheitrum holds Ms, Bs, Electrical Engineering / Computer Science from Lehigh University.

Company email context

Email format at Atessa, Inc.

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{first_initial}{last}@atessainc.com
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AeroLeads found 1 current-domain work email signal for Mark Scheitrum. Compare company email patterns before reaching out.

Profile bio

About Mark Scheitrum

Mark Scheitrum brings better than twenty years of successful senior management experience within the electronics industry across a wide variety of technology areas (Systems, EDA, SOC, IP and Processor), markets (DoD, Communications, Industrial and Consumer), delivering pioneering products and capabilities with industry-leading companies.As Business Director and head of R&D, Design Services and Engineering Organizations, Mark has successfully developed and sustained multiple product, business and service lines and established engineering capabilities world-wide. His experience can reduce the risk and accelerate the time to revenue for any organization, ultimately leading to compelling liquidity events for company stakeholders. Mark’s expertise in organizational development and turn-around, solution architecture and execution, operational excellence and broad technical expertise continues to serve his Companies well.Specialties: Senior-Level Technical Management, R&D, Engineering and Design Services Management, Business Development, Gov’t, DoD and Commercial Programs,Product Definition and Development, Key Account Liaison, Solution Architect, Strategic and Business Planning,Embedded HW/SW Systems, Embedded Processors, SOC ASICs, Simulation & Modeling, RTOS, Security, Anti-Tamper, Training, Business Procedures and Practices, World-Wide Delivery Team Management, Intellectual Property Management, Secret Clearance

Listed skills include Rtos, Embedded Systems, Security, R&D, and 1 others.

Current workplace

Mark Scheitrum's current company

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Atessa, Inc.
Atessa, Inc.
COO
pleasanton, california, united states
Website
Employees
9
AeroLeads page
8 roles

Mark Scheitrum work experience

A career timeline built from the work history available for this profile.

Coo

Current

Founded in mid-2010 to help system developers meet critical AT requirements and address global supply chain security challenges, Atessa reached profitability in Q1 2011.Atessa, Inc., provides Trusted system IP with anti-tamper (AT) technology. Our products and services enable system developers to meet AT requirements and address global supply chain.

Nov 2010 - Present

Vice President Engineering

Direct an organization providing solutions, products and design services to DoD and Industry for long-lived electronic systems modernization and sustainment.Key customers; Key programs: F16 CPDG, Bradley PIB and TDCUII, Raytheon Standard Missile, Raytheon ALR67, Navy AYK14 upgrade, Mil-Std 1750A-FB/FX processor upgrade and othersPioneered and Productized.

Jan 2003 - Aug 2010

Vice President Systems Engineering

Chameleon Systems, Inc

Directed all system engineering activities for a venture funded re-configurable streaming data processor company including applications engineering, design services, strategic partnership programs, third party developer programs, systems architecture, system validation and product design Developed and managed strategic customer and commercial design.

Jan 2000 - Jan 2002

Group Director, Design Services

Cadence Design Systems, Inc

Originated and grew system design service delivery capability from 1 (self) to worldwide (U.S., U.K., France, Japan) design centers in 24 months.Defined and established successful System-On-Chip design services organization for Multimedia systems. Pioneered concepts of SOC integration platforms and rapid FPGA prototyping services for SOC design. Industry.

Jan 1995 - Jan 1999

Vice President Development

Cpu Technology Inc

Responsible for architecture, products and business development of advanced processors and systems.Developed rapid design flow around system-level simulation, HW/SW co-simulation and cycle accurate processor models for commercial processors.Managed development of multiple product lines and services for government and commercial customers.Key customers.

Jan 1992 - Jan 1995

Director Of Asic Engineering

Lsi Logic Corp

Responsible for ASIC engineering organization for LSI Logic PC Chipset business.Developed successful line of PC and graphics chipsets (grew revenue from $12M to over $75M annually).Architected and led development of first industry successful 'single chip' PC core logic component (3M+ Units). Managed development of PC Chipsets for 286, 386 and 486 based.

Jan 1989 - Jan 1992

Director Of Systems Engineering

Daisy Systems Corp

Led hardware and systems design organization for industry pioneer CAE engineering workstation company.Member of founding team, developed workstations that provided product foundation for company from startup through revenue of over $50M annually and headcount of over 800. Defined and developed many industry first EDA and engineering workstation products.

Jan 1981 - Jan 1988

Microprocessor Design Project Leader

Intel Corp

Microprocessor design team leader for general-purpose microprocessors and microcontrollers. Member of architecture definition team for i80486 Intel processor.Co-designer of world's first 16-bit embedded microcomputers, the i8061 and i8096 Designed and prototyped, delivered, installed and supported

Jan 1978 - Jan 1981
Team & coworkers

Colleagues at Atessa, Inc.

Other employees you can reach at atessainc.com. View company contacts for 9 employees →

1 education record

Mark Scheitrum education

FAQ

Frequently asked questions about Mark Scheitrum

Quick answers generated from the profile data available on this page.

What company does Mark Scheitrum work for?

Mark Scheitrum works for Atessa, Inc..

What is Mark Scheitrum's role at Atessa, Inc.?

Mark Scheitrum is listed as COO at Atessa, Inc..

What is Mark Scheitrum's email address?

AeroLeads has found 1 work email signal at @atessainc.com for Mark Scheitrum at Atessa, Inc..

What is Mark Scheitrum's phone number?

AeroLeads has found 5 phone signal(s) with area code 408, 619, 925 for Mark Scheitrum at Atessa, Inc..

Where is Mark Scheitrum based?

Mark Scheitrum is based in San Jose, California, United States while working with Atessa, Inc..

What companies has Mark Scheitrum worked for?

Mark Scheitrum has worked for Atessa, Inc., Cpu Tech, Chameleon Systems, Inc, Cadence Design Systems, Inc, and Cpu Technology Inc.

Who are Mark Scheitrum's colleagues at Atessa, Inc.?

Mark Scheitrum's colleagues at Atessa, Inc. include Elmer Palma, Edward King, Alan Smith, Vanessa Hernandez, and Nik Lewis.

How can I contact Mark Scheitrum?

You can use AeroLeads to view verified contact signals for Mark Scheitrum at Atessa, Inc., including work email, phone, and LinkedIn data when available.

What schools did Mark Scheitrum attend?

Mark Scheitrum holds Ms, Bs, Electrical Engineering / Computer Science from Lehigh University.

What skills is Mark Scheitrum known for?

Mark Scheitrum is listed with skills including Rtos, Embedded Systems, Security, R&D, and Business Development.

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