Mark Scheitrum Email and Phone Number
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Mark Scheitrum brings better than twenty years of successful senior management experience within the electronics industry across a wide variety of technology areas (Systems, EDA, SOC, IP and Processor), markets (DoD, Communications, Industrial and Consumer), delivering pioneering products and capabilities with industry-leading companies.As Business Director and head of R&D, Design Services and Engineering Organizations, Mark has successfully developed and sustained multiple product, business and service lines and established engineering capabilities world-wide. His experience can reduce the risk and accelerate the time to revenue for any organization, ultimately leading to compelling liquidity events for company stakeholders. Mark’s expertise in organizational development and turn-around, solution architecture and execution, operational excellence and broad technical expertise continues to serve his Companies well.Specialties: Senior-Level Technical Management, R&D, Engineering and Design Services Management, Business Development, Gov’t, DoD and Commercial Programs,Product Definition and Development, Key Account Liaison, Solution Architect, Strategic and Business Planning,Embedded HW/SW Systems, Embedded Processors, SOC ASICs, Simulation & Modeling, RTOS, Security, Anti-Tamper, Training, Business Procedures and Practices, World-Wide Delivery Team Management, Intellectual Property Management, Secret Clearance
Atessa, Inc.
View- Website:
- atessainc.com
- Employees:
- 9
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CooAtessa, Inc. Nov 2010 - PresentFounded in mid-2010 to help system developers meet critical AT requirements and address global supply chain security challenges, Atessa reached profitability in Q1 2011.Atessa, Inc., provides Trusted system IP with anti-tamper (AT) technology. Our products and services enable system developers to meet AT requirements and address global supply chain security challenges. Unique to Atessa, our solutions secure Critical Program Information (CPI) within existing and new systems, and provide the ability to rapidly address security moving forward. Using our soft IP solutions, developers and program managers can rapidly update security in the field between design cycles.IP cores from Atessa make security practical and scalable: our solutions are ultra low impact in size, weight, power, and cost. In addition, our IP is fully supported by industry-leading secure visibility tools and insertion/application services.
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Vice President EngineeringCpu Tech Jan 2003 - Aug 2010Direct an organization providing solutions, products and design services to DoD and Industry for long-lived electronic systems modernization and sustainment.Key customers; Key programs: F16 CPDG, Bradley PIB and TDCUII, Raytheon Standard Missile, Raytheon ALR67, Navy AYK14 upgrade, Mil-Std 1750A-FB/FX processor upgrade and othersPioneered and Productized Methodologies for Compatible and Secure Upgrade of Long-Lived SystemsDirected development of successful real-time system modeling environment, SystemLabPSDelivered multiple first-silicon successful System-On-Chip ASIC solutions for critical system applications with IBM / TAPO, Jazz Semi, Epson, ChipX, LSI Logic and others using COT flow and multiple ASIC flows.Provide primary technical interface with customers and vendors for programs and services.Responsible for all technical aspects of business development including solutions architecture, SOW development, costing, risk mitigation, issue resolution and resource management. -
Vice President Systems EngineeringChameleon Systems, Inc Jan 2000 - Jan 2002Directed all system engineering activities for a venture funded re-configurable streaming data processor company including applications engineering, design services, strategic partnership programs, third party developer programs, systems architecture, system validation and product design Developed and managed strategic customer and commercial design services delivery for key customers including: Motorola, Lockheed, Ericsson, Nortel, Alcatel, Eyretel, WirelessOnline, othersProjects included: 3G wireless BTS apps: (rake receiver, path searcher, antenna array correlation, turbo and viterbi codecs), software defined radio apps, development boards, etc.Established architecture board to define architecture / products for streaming data processing.Recruited and sponsored technical advisory board of key academic and industry advisors.
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Group Director, Design ServicesCadence Design Systems, Inc Jan 1995 - Jan 1999Originated and grew system design service delivery capability from 1 (self) to worldwide (U.S., U.K., France, Japan) design centers in 24 months.Defined and established successful System-On-Chip design services organization for Multimedia systems. Pioneered concepts of SOC integration platforms and rapid FPGA prototyping services for SOC design. Industry recognized VLSI Vision SOC design program completed from concept to product-in-channel in less than 1 year: Proposed, architected and led design of single-chip motion video camera device w/ compression and USB interface for VLSI Vision, Scotland (over 500,000 cameras sold through Creative Labs).Completed multiple successful ($M+), service engagements for architecture and design of SOC products for commercial system companies. Key customers: Fujitsu Microelectronics, Applied Magic, OKI Semiconductor, Mitsubishi, Media 100, otherKey projects: Prosumer video editor, HDTV video processor chips. MPEG2 decompression chip and simulation environment, Multimedia SOC Integration Platform methodology, Professional video editing devices.Initiated or evaluated partnership/acquisition of IP and service capabilities worldwide (Altera, Sand, ARM, MIPS, Sarnoff Labs Jacobs-Pineta, other).Instrumental in defining and booking over $200M in services business throughout the company.
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Vice President DevelopmentCpu Technology Inc Jan 1992 - Jan 1995Responsible for architecture, products and business development of advanced processors and systems.Developed rapid design flow around system-level simulation, HW/SW co-simulation and cycle accurate processor models for commercial processors.Managed development of multiple product lines and services for government and commercial customers.Key customers: IBM, AMD, NEC, VLSI Technology, LSI Logic, Navy, Honeywell, other.Key projects: PC chipsets for memory control and north-bridge, Processor validation suite and services for 386, 486 & Pentium architectures, 32 bit instruction set architecture upgrade for Mil-Std 1750A avionics processor
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Director Of Asic EngineeringLsi Logic Corp Jan 1989 - Jan 1992Responsible for ASIC engineering organization for LSI Logic PC Chipset business.Developed successful line of PC and graphics chipsets (grew revenue from $12M to over $75M annually).Architected and led development of first industry successful 'single chip' PC core logic component (3M+ Units). Managed development of PC Chipsets for 286, 386 and 486 based PCs.Re-engineered company's IC development methodology including system level simulation and prototyping to achieve first-pass silicon success.Successfully added graphics chip design engineering staff and capability.Liaison with LSI Logic IP and process development groups.Performed business development throughout Europe and Asia.
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Director Of Systems EngineeringDaisy Systems Corp Jan 1981 - Jan 1988Led hardware and systems design organization for industry pioneer CAE engineering workstation company.Member of founding team, developed workstations that provided product foundation for company from startup through revenue of over $50M annually and headcount of over 800. Defined and developed many industry first EDA and engineering workstation products and features. Key products: First engineering workstation, Dual user workstation, 'Logician-D', First Color graphics workstation, First Multi-processor workstation and other.Established all HW engineering infrastructure, ECO procedures, documentation control and product transfer procedures.Managed hardware product development for all product lines of workstations, simulation accelerators, Place & Route engine, PMX (physical modeling accelerator), and peripherals.
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Microprocessor Design Project LeaderIntel Corp Jan 1978 - Jan 1981Microprocessor design team leader for general-purpose microprocessors and microcontrollers. Member of architecture definition team for i80486 Intel processor.Co-designer of world's first 16-bit embedded microcomputers, the i8061 and i8096 Designed and prototyped, delivered, installed and supported
Mark Scheitrum Skills
Mark Scheitrum Education Details
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Electrical Engineering / Computer Science
Frequently Asked Questions about Mark Scheitrum
What company does Mark Scheitrum work for?
Mark Scheitrum works for Atessa, Inc.
What is Mark Scheitrum's role at the current company?
Mark Scheitrum's current role is Senior Technology Executive at Atessa Inc..
What is Mark Scheitrum's email address?
Mark Scheitrum's email address is ms****@****ail.com
What is Mark Scheitrum's direct phone number?
Mark Scheitrum's direct phone number is +140844*****
What schools did Mark Scheitrum attend?
Mark Scheitrum attended Lehigh University.
What skills is Mark Scheitrum known for?
Mark Scheitrum has skills like Rtos, Embedded Systems, Security, R&d, Business Development.
Who are Mark Scheitrum's colleagues?
Mark Scheitrum's colleagues are Alan Smith, Vanessa Hernandez, Edward King, Nik Lewis, Elmer Palma.
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