Mars Huang Email and Phone Number

Led 28nm node technology defect reduction initiatives: 1 Spearheaded team for 28nm products defect reduction plan, focusing on front-end process improvements. 2 Achieved 4.5% CP yield increase for 28nm node technology (IE certificated). 3 Optimized STI CMP process, resulting in $300 million savings and 12 headcount reduction. 4 Resolved critical reliability issues including HK missing and STI u scratch-induced burn out problems. 5 Directed poly etcher and contact hole blind defect reduction plans, addressing 28nm killer defects.• Managed 28nm node technology process cost reduction project: 1 Conducted 28nm process flow analysis, identifying skip/merge opportunities for 2% cost savings. 2 Led wafer inspection tool performance comparison, resulting in $45 million savings through AMAT UVison 5 implementation. 3 Developed KLA recipe setup system, improving engineer productivity with 24/7 recipe management.• Implemented advanced inspection and analysis systems: 1 Introduced Magma CAD-based inspection technology for enhanced defect analysis. 2 Coordinated AMAT and TSMC engineers to develop filter algorithms for Magma's EDA software integration. 3 Deployed Automatic Defect Classification (ADC) system, achieving 90% accuracy and 80% manpower savings.• Implemented Automatic Defect Classification (ADC): • ADC systems typically work by: 1 Collecting data: Gathering images of defects from SEMVision G7 review tools. 2 Pre-processing: Enhancing the quality of the images by adjusting brightness, contrast, and removing noise. 3 Feature extraction: Identifying relevant features in the images that can be used to describe the defect. These features may include shape, size and location. 4 Training: Using machine learning genetic algorithms (GAs) to train a model on a labeled dataset of defects.

• Led flash products yield improvement initiatives: 1 Increased 0.18um flash products cp yield to 88%, meeting customer goals by resolving poly line end breakage. 2 Maintained 0.25/0.35um flash products cp yield above 91%.• Managed new product transfers and defect reduction: 1 Improved IR's discrete High voltage product cp yield to 95% within 7 months, earning high customer praise. 2 Increased Panasonic's LCD driver IC cp yield to 93% in 3 months.• Developed critical analysis systems: 1 Created WAT (Wafer Acceptance Test) mapping analysis system, streamlining engineer workflow for failure rate analysis and reporting. 2 Implemented defect library system, categorizing defects by technology and providing operator reference material for main stream FAB operations. 3 Personally developed web-based interfaces for both systems, significantly reducing engineer workload.

• Improve and enhance the efficiency and productivity of equipment: 1 Lead engineer for CVD equipment, managing a fleet of 30+ tools. 2 Improved equipment uptime by 5% through implementation of predictive maintenance strategies. 3 Developed and implemented new recipes for advanced node processes, reducing defects by 12%. 4 Collaborated with process engineers to optimize WSIX thin film uniformity, achieving <1% within-wafer variation. 5 Maintained and troubleshot W CVD systems, ensuring 95% equipment availability. 6 Conducted root cause analysis on equipment failures, reducing MTBF by 30%.• Led implementation of equipment alarm system: 1 Managed team to integrate alarm system, notifying on-duty engineers of equipment issues. 2 Improved equipment availability and uptime through proactive maintenance.• Collaborated with R&D on Cu process studies: 1 Maintained and evaluated cu ECP / CMP / low k dielectric material equipment. 2 Copper process research and development project won the Chairman Morris Chang Award.