Perform power integrity and power delivery analysis, design, measurement and debug in support of Cloud Computing business.

Perform post silicon power thermal and performance validation of Xeon class Intel Architecture SOCs, Including verification of Thermal Design Power, Thermal Margin, Memory, IO, and Core performance metrics.

• Key Skills; Power Integrity, Power Delivery, Signal Integrity, Power SI, Power DC, HSPICE, Simulation, Hardware Design, Circuit Analysis, Debug, VNA, TDR, Oscilloscope, Schematic Entry, Layout Review• Responsible for the design and development of Internet of Things hardware platforms, including validation platforms and customer reference boards.• Focused on power delivery and analog circuit design and simulation• Own the implementation of all power related circuitry including voltage regulators, automated margining circuitry, ADC based voltage and current monitoring.• Strong contributor to platform architecture decisions for both analog and digital domains

• Responsible for the power integrity performance of multiple power rails across several generations of Intel microprocessor packages and motherboards• Developed nearly a decade of expertise using the Cadence Sigrity Power SI, Power DC, and Speed 2K suite of analysis tools• Refined and optimized package and motherboard routing, via placement, capacitor selection, placement, and routing to meet power integrity requirements with minimal cost• Extracted S parameters of package and motherboard power routing using Power SI extraction mode to run both frequency domain impedance simulations and time domain transient simulations in HSPICE• Employed Power SI Spatial Mode to generate impedance profiles directly in Power SI• Designed package inductors for FIVR (Fully Integrated VR) utilizing Power SI 3D FEM Full Wave for S parameter extraction and Power DC for DC resistance determination• Developed a complete time domain FIVR switching model in Speed 2K as well as a non-switching averaged model, showing correlation to the internal partial element equivalent circuit model• Preformed FIVR efficiency, ripple, firing order and transient droop prediction simulations• Utilized Power DC for voltage drop, resistance, sense point location, current density checking, hotspot identification, via and pin current sharing analysis• Macro-modeling using IDEM Works and Broadband Spice creating SPICE models from S parameters• Performed lab measurements of power network impedance Z(f) using IFDIM (Integrated Frequency Domain Impedance Measurement) and correlated this to simulated predictions• Partial Element Equivalent Circuit modeling of power delivery network using Ansoft Q3D

Setup lab capabilities to perform RF measurements using on wafer probing of circuit components including RF amplifiers, mixers, and switches.

Performed high speed signal analysis and simulation on various interfaces including PCI express, SDRAM memory channels, and proprietary high bandwidth serial interfacesCreated routing guidelines and contributed to industry specifications