Vincent Martinez Email & Phone Number

Toulouse, Occitanie, Fr

Eindhoven, Noord-Brabant, Nl

V2X standardization engineer: active participation at ETSI ERM TG37 (rapporteur of TR 103 688), ETSI ITS WG4, IEEE 802.11bdAlso active on:- V2X technical lead (algorithms, SW & HW Arch)- Wireless BMS- AI & Signal processing expert (incl. Radar)

Eindhoven, Noord-Brabant, Nl

- V2X standardization (ETSI ERM TG37, ETSI ITS WG4, IEEE 802.11bd)- V2X technical lead (algorithms, SW & HW Arch)- AI & Signal processing expert (incl. Radar)

Eindhoven, Noord-Brabant, Nl

Technical expert and lead for DFE solution on NXP AFD4400 device.• Algorithms innovation, definition and validation through performance simulations, implementation specification, and coordination of the development team. Deep knowledge of algorithms like DPD (Digital Pre Distortion), CFR (Crest Factor Reduction), Massive MIMO and Beamforming, DUC, DDC, QEC, time-synchronization• Real-time embedded SW Architect, with SW (system) partitioning to optimize performance, power consumption, costs. Includes functional mapping, MIPS and memory footprint, multi-core optimization• Frequent visits to tier-1 customers in Europe & China for presentations and customer supports• Lab measurements, validation of NXP DFE solution (PAPR, ACLR, ACP, EVM on R&S tools)• Work within a worldwide multicultural team.

Austin, Texas, Us

Algorithmic lead for Freescale Uplink Layer1 eNodeB SW.• Modem Algorithms design: Drive the design, validation and DSP implementation of advanced modem algorithms, including MIMO Equalization, Turbo/SIC schemes, Channel estimation, time offset and frequency offset measurements. Owner of Uplink Matlab Radio Link Simulator• Multicore SW architect. Define functional mapping for LTE Layer-1 over complex multi-core SoC such as Freescale QorIQ Qonverge B4860 for a variety of deployment and customers. Memory, MIPS and latency optimization expertise.• HW Arch definition contribution. SoC definition (number of cores, memories & buses, accelerators requirements)• Customer interface: Weekly communication, technical meetings with major Tier1 OEMs (Alcatel-Lucent, ZTE …). Workshops, presentations of Freescale’s devices and PHY modules/stacks.• Technical lead for a 10+ people project

Austin, Texas, Us

LTE & LTE-Advanced Layer1 DSP System Engineer> In depth knowledge of LTE and LTE-Advanced 3GPP Standard (36 series)> Advanced receivers algorithms (SIC, channel estimation and many more)> System knowledge from RF up to Layer2> Freescale DSPs & StarCore cores

Austin, Texas, Us

Analysis and comparison of the methods and algorithms available for Digital PreDistortion (DPD) for RF HPA (High Power Amplifiers) used in third generation (UMTS) mobile telecommunication base stations (3G W-CDMA): Volterra Series, Neural Networks, Mixed Effects Models, 2D LUT, Memory Polynomials, Wiener and Hammerstein Models. Programming in Matlab of a Digital Pre Distortion model based on Volterra Series and validation on the real RF DPD bench.

Mathematical And Statistical Modeling

Mathematics & Computer Science