Marty Perrigo Email & Phone Number

New York, Ny, Us

System and hardware architecture, hardware development, FPGA development

System and hardware architecture, hardware development, FPGA development

Santa Clara, California, Us

Transitioned to AMD through acquisition of ATI Research. Responsible for architecture, design and verification of Video Processing and Frame Rate Conversion (FRC) chips. Designed stream manager which handled all data streams passing through FRC chip (U.S. Patent Number 7,822,891). Provided integration support to about 5 different customers using our chip in their board designs. Performed characterization of chip over process, voltage and temperature. Supported firmware team to develop implementation for multiple customer applications.

Santa Clara, California, Us

Lead engineer from concept to design and implementation with the ability to find creative solutions to problems in areas of expertise. Designed and verified 128-bit SIMD/reduction DSP engine with instruction set tailored to video processing with support for streaming data types, with enhancements to the instruction set each generation. Designed and developed a new (0.18um 0.15um and 0.13um CMOS) 500MHz DLL with differential common self-bias current mode with low jitter control circuitry and automatic current range calibration for process and power supply variations (U.S. Patent Number 6,411,142 B1, and 6,903,586 B2). Designed and developed three new digital PLLs (0.18um 0.15um and 0.13um CMOS, input 33MHz/output 264MHZ, 528MHZ or 1056 MHz, input 400KHz/output 400MHz, input 2MHz/output 600MHz) with differential common self-bias current mode, with fast lockup/ low jitter circuitry and automatic current range calibration for process and power supply variations (U.S. Patent Numbers 6,646,512 B2, 6,859108 B2). Completed characterization of Memory Compiler generated memory designs using HSPICE and HSIM with followup testing in the lab.

Dallas, Tx, Us

Design engineer Memory Products Division. Flash EPROM Memory design.Engineer in design, development, and integration of new concepts. Designed and developed custom circuitry for several 1, 2, and 4 megabit Flash EPROM, including a custom chip for Ford Motor company for use in their Powertrain Electronic Controller. Developed floorplans and implemented physical design of Flash EPROM chips. Maintained standard cell library for use in Flash EPROM designs. Led physical design effort with newly developed Mentor Graphics Universal Place and Route tool.

Armonk, New York, Ny, Us

Summer Internship at IBM in Burlington VT