3 years of experience in Analog and Mixed-Signal Mask Design. Good proficiency in development of block-level analog layouts including floorplanning, placement, routing, and physical verification. Extensive use of Cadence Virtuoso L/XL, Mentor Calibre and StarRC to perform DRC, LVS, ERC, PEX, DFM, client-specific DRC checks such as antenna and well-antenna, PG check, voltage markers, etc.Experience in industry with planar technologies (TSMC 22nm, GlobalFoundries 130nm BCD), and training on FinFET technologies (TSMC-16 and Intel-22). Development of several sub-blocks, such as logic cells, digital soft starter, charge-pump, senseamp, amplifiers, low-power comparator, oscillator, bandgap, reverse current protector. Knowledge of triple well devices, DNW isolation, good layout practices to avoid issues with density, electromigration, crosstalk and latch-up, as well as meeting IR and ESD constraints required by the client.Production of Layout Review documentation for finished IPs.Intermediate proficiency in Bash, PERL, TCL, Python. Basic knowledge of Synopsys ICC2 for Physical Design.