Lead Hardware Engineer
Current• Led team of engineers in delivering PoC and MVP of a hardware-based post-quantum solution.• Oversaw software architecture and verification planning.• Developed an accelerator device boosting performance by 56x over single core.• Integrated PCIe Gen4 x16 into architecture. • Implemented RO TRNG and developed a novel method for unbiased generation.• Created abstraction framework to integrate multiple tools from various EDA vendors, encompassing Xcelium, Vivado, Questa, Quartus and Verilator.• Developed BFM adhering to the AvalonMM/ ST and AXI protocols.• Implemented SystemVerilog DPI in the verification environment to facilitate communication between UVM classes and C functions.• Introduced CI/CD pipelines in project flow.• Implemented coverage analysis and sva properties to the verification environment.• Designed abstraction module to hide a memory hierarchy containing DDR4 and internal caches.• Created synchronization mechanism for high-throughput serialization.• Created a custom protocol for packet-based batch communication.• Applied OOP methodology in tb and guided verif team on a UVM-based flow.• Devised alternatives using USB bulk mode and UTMI+ protocols.