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20+ years in Design and Verification with a heavy emphasis on minimizing process while maximizing quality and throughput.DevOps is important and a necessity but more is needed? Every single company is "doing DevOps" or "doing hardware DevOps". What else can you do to put yourself above your competitors?I have 20+ years of extensive real-world experience answering questions like:1) What's the fastest and most efficient method of turning SystemVerilog code into reliable silicon and out the door into customer hands?2) When does slowing down individual engineering velocity actually increase project velocity?3) What's cost/benefit of having an internal IT/CAD managed development environment vs changing your processes to use unmodified COTS/OSS solutions? Hint: If your answer involves "wrapper scripts", you might want to revisit your setup.4) What information does your C-suite really not need to see? Nightly functional and code coverage will just confuse and distract. They care about trends, outliers and blocking dependencies.5) Why is it a horrible idea to have a member of the team designated as the "branch merge-monkey"?6) DevOps is great, and indeed a necessity, but it's a process, not a checkbox on a marketing slide. DevOps is the first step; an initial requirement that every company is using these days.7) Why is it sometimes a terrible idea to just give engineering more storage space for development?8) IT _loves_when engineering develops on shared NFS mounts as it makes some things easier, but it also introduces small race conditions in the build system that can result in random, and very confusing, failures. How to avoid those?The question I think is actually the most important is:If you took these people out for "refreshments": 1) the developers/engineers writing the code 2) management minding the deadlines 3) IT responsible for resources 4) the QA folks ensuring things actually work as expected 5) marketing folks trying to sell the thing and talk honestly, what could they accomplish together?If that's where your thoughts are, we might be on the same page.
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Design EngineerAmd Feb 2022 - PresentSanta Clara, California, Us -
Senior Firmware EngineerMicron Technology Nov 2017 - Oct 2022Boise, Idaho, UsSetup Mesos and Docker cluster to create guaranteed consistent environments for running simulations and with guaranteed failure reproducibility. Wrote Mesos framework, in python. -
Design EngineerXilinx Nov 2019 - Feb 2022San Jose, Ca, Us -
Senior Principal EngineerBurlywood, Llc Mar 2016 - Jun 2017Designed (with verilog), verified (with SV and UVM), and validated (with Xilinx FPGAs) AXI masters, slaves and interconnects.Wrote OVL assertions to check transaction/operations in FIFOs, AXI, GPIO and other blocks.Wrote hardware abstraction (HAL) classes in C++ for firmware to communicate with custom hardware.Wrote unit level tests for firmware using python, unittest/testtools and hypothesis.Set up continuous integration flow with Jenkins and gitlabSet up linux lab machines as configuration controlled (using git with planned migration to salt), PXE booted “single sign-on” against a Windows AD domain controller.Set up a small Hadoop cluster.Set up monitoring system on servers using OpenTSDB and grafana.
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Staff Asic Verification Engineer & DevopsMicron Mar 2012 - Oct 2015Boise, Idaho, UsData center architect for Micron's (at the time) newest data center. Micron leveraged many of the trailblazing ideas we developed at the remote data center and incorporated them into the other corporate data centers.Architected and managed the development environment used by 150+ developers and engineers across multiple sites.Member of the verification architecture and methodology group that designed the verification base classes and drove UVM best practices through the division. Created Veloce-friendly, UVM-compliant, event-driven testbenches and UVCs.Wrote constrained random tests in UVM.Wrote python scripts to compile, simulate, and manage branch merge and regression and reporting.Wrote python and bash scripts to collect, manage and publish status and coverage to internal wiki.Wrote python scripts and worked with validation group to incorporate Veloce TBX into flow.Analyzed and improved inefficient and/or resource hungry SOC tests. (IE: unnecessary package imports, coverage collection on every clock rather than on events, etc.)Created and managed the fully automated branch merging infrastructure.(The Jenkins plugins hadn't yet been created.) Set up dynamic branch and trunk locking interaction between jenkins and subversion servers.Integrated register map wiki regeneration into the trunk merging flow. Coordinated with managers and engineers to automate and enforce simulation license priorities.Created and integrated heuristics database into flow to start longer simulations before shorter onesSetup and managed subversion proxies at each data center to speed repository access.Setup server farm monitoring.
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Data ArchitectConsistent State Sep 2010 - Mar 2012Denver, Co, UsAdministrating, designing, architecting and performance tuning of: * large 100+ million daily transaction databases* multi-terabyte in-house data warehouses* world-wide distributed databases.Set up server farm monitoring using cacti and nagios -
Design EngineerSeakr Engineering Jul 1998 - Aug 2009Centennial, Colorado, UsResponsibilities on most projects were very wide ranging. They included design, test, writing test procedures and test plans, writing and verifying requirement matrices, board level design, FPGA level design, simulation and verification, integration work and formal vibration, EMI and functional testing and customer support and interaction. Most projects were requirements based and involved design reviews with the customer and requirement matrices to ensure all requirements were fulfilled and formally tested. I worked on multiple different designs in over half a dozen satellites all with on-orbit success.Verified IP (Internet Protocol) module for Internet Router In Space (IRIS) program using mixed VHDL and Verilog.Verified PCI cores (master and target).Verified PCI to IDE bridge FPGA using VHDL.Verified SDRAM and DDR Controller FPGA using VHDL.Did board design and schematic capture of I/O boards for satellite data recorders.Did lab debug, worked with protocol analyzers, oscilloscopes, etc.Designed, verified and validated multiple FPGAs.Rewrote build system so multiple projects, including external co-subcontractors, could inter-operate.Led a multi-year effort to create and build a common reusable library of verification components as well as verified and validated logic cores and blocks.Implemented a LAMP solution that allowed engineering tools to connect to ERP system.Set up an OpenMOSIX cluster to load balance simulations across server farm
Matt Dew Skills
Matt Dew Education Details
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University Of Colorado BoulderComputer Science -
云南大学 (Yunnan University, Kunming, China)汉语 (Mandarin Chinese)
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University Of Colorado BoulderComputer Engineering
Frequently Asked Questions about Matt Dew
What company does Matt Dew work for?
Matt Dew works for Amd
What is Matt Dew's role at the current company?
Matt Dew's current role is Design/Verification Engineer.
What is Matt Dew's email address?
Matt Dew's email address is ma****@****rce.org
What schools did Matt Dew attend?
Matt Dew attended University Of Colorado Boulder, 云南大学 (Yunnan University, Kunming, China), University Of Colorado Boulder.
What skills is Matt Dew known for?
Matt Dew has skills like Verilog, Debugging, Embedded Systems, Asic, Fpga, Systemverilog, Perl, Hardware Architecture, Modelsim, Linux, Functional Verification, Uvm.
Who are Matt Dew's colleagues?
Matt Dew's colleagues are Srikanth Kakkirala, Ritesh Sachan, Varsha Agarwal, Srishailam Boggula, Ken Takeuchi, Kar Choong Kwa, Akhil Bhujle.
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