Matteo Vit Email & Phone Number

Cambridge, Cambridgeshire, United Kingdom

Cambridge, United Kingdom

ASIC/FPGA design and verification (Xilinx and Altera; ISE/Vivado and Quartus; verification with UVVM, Cototb; QEMU-FPGA co-simulation, AI accelerators). Devops for FPGA.AI architecture design for RTL implementation.Hardware design (FPGAs, microprocessors/microcontrollers, digital video I/Os, mixed-signals (ADCs, DACs), switching DC/DCs, FMC boards, high speed (PCIe, DDRx)).Linux device drivers.Yocto customisation (new packages, patches, etc) and integration with CI.Zephyr.Test systems design and implementation (Python/RobotFramework, NI VISA instruments integration, PyQT GUI).Member of the IoT Security Foundation.

Cambridge, United Kingdom

Technology development and creation of demos for potential clients/partners or tradeshows.Development of Innovative algorithms (mainly Numpy).Creation of a multi-disciplinary engineering team (electronics, FPGA, DSP and Android system/apps).Technical authority and technical lead for the engineering team.Design and code reviews.Mentoring of junior engineers.

Cambridge, United Kingdom

Technical authority for FPGA and digital hardware development.New technologies and processes champion (i.e. adoption of SystemVerilog/UVM, Altium integration with company database, continuous integration for FPGA development, etc).Interim project manager (multiple projects, team size up to 6 engineers).FPGA design and verification (Xilinx and Lattice). Embedded system design (Altium). U-boot and Linux hacking.Bespoke communication protocol design and implementation.End of line test system design and implementation (Python/RobotFramework).Co-author of 4 patents.

Systems engineer and WBE responsible at Selex Galileo.

Systems engineer. In charge of various flight simulator WBEs. Defining and designing sub-systems and architecture for simulation system either in the concept or the development phase. Leading the technical and engineering activities required by the specific role. Reviewing the sub-system designs and current architecture choices, documenting the agreed interfaces and all associated activities.Activities scheduling (using Microsoft Project).System modelling with Matlab/Simulink/Stateflow. Sound and communications model development with ASTi tools.Writing technical documentation compliant with MIL-STD-498.

Project leader for: a vehicle tracking and safety system, a ticket vending machine, home automation project. Development of system level designs from customer proposals. Project reviews. System qualification prior to production sign off. Systems design (mechanical, electronic, electrical, software). 2D and 3D mechanical design. Cabling harness design. Technical support. Internal and outsourced resources coordination.

FPGA design with VHDL and Verilog (Xilinx Virtex4 and Lattice XP2). Embedded system design with PPC, ARM, AVR32 and x86 processor. Linux device driver programming. Bootloader hacking (u-boot). Schematic entry. SoC design. Real-time video application with AVR32 (http://www.dave.eu/index.php?page=3#CS1). Student mentoring (BSEE thesis of M. Geromin “Embedded system design on FPGA with 2D hardware acceleration”, http://www2.units.it/ingeln/tesi/2009/video_hw_accelerator_on_fpga.ppt).

Cluster installation, hardware configuration, software installation and customization. Tuning, testing and benchmarking. Customer support (remote and on site). Diskless and live cd solutions development. Consultant coordination. PLC-based automation system design. Rack power distribution unit design. One cluster rated at Top500 (http://www.top500.org/system/8112).

FPGA remote update systems design. Digital design with VHDL and Quartus II from Altera. Altera Nios II peripheral design and its device driver. PCI-X core interfacing. C and Perl programming. USB interfacing with FTDI devices. Linux low level application developing.

Master Of Science (Msc), Electronic Engineering

Dissertation titled "Remote update systems for FPGA in High Performance Computing applications"

Electronics