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Matteo Vit is listed as Director / Principal Design Engineer at Starware Design at Starware Design Limited, a company with 1 employees, based in Greater Cambridge Area, United Kingdom, United Kingdom. AeroLeads shows a work email signal at starwaredesign.com and a matched LinkedIn profile for Matteo Vit.
Matteo Vit previously worked as Director / Principal Design Engineer at Starware Design Limited and Engineering Director at Cambridge Touch Technologies Ltd. Matteo Vit holds Master Of Science (Msc), Electronic Engineering from Università Degli Studi Di Trieste.
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I am an electronics engineer with over a 20 years of work experience in a variety of markets: from high performance computing to industrial, from home automation to automotive, from defence to power electronics.After working for several companies ranging from start-up to big multinational, I have decided to set up my own company, Starware Design, to offer my expertise to Clients seeking design and consulting services for cutting edge technologies.I have a track record of technology innovation (co-author of 5 patents, hackaton winner) plus new processes/methodologies introduction.I work comfortably in roles ranging from architect/technical leadership to more hands-on/detailed design. My specialities are:- embedded systems architecture design- ASIC/FPGA design and verification- embedded Linux and Zephyr- AI/ML- hardware design (high speed schematic and layout)- project leading / project management- multidisciplinary projects (combination of hardware, FPGA, software and mechanical)Member of the IoT Security Foundation
Listed skills include Embedded Systems, Fpga, Vhdl, Electronics, and 46 others.
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Cambridge, United Kingdom
ASIC/FPGA design and verification (Xilinx and Altera; ISE/Vivado and Quartus; verification with UVVM, Cototb; QEMU-FPGA co-simulation, AI accelerators). Devops for FPGA.AI architecture design for RTL implementation.Hardware design (FPGAs, microprocessors/microcontrollers, digital video I/Os, mixed-signals (ADCs, DACs), switching DC/DCs, FMC boards, high.
Cambridge, United Kingdom
Technology development and creation of demos for potential clients/partners or tradeshows.Development of Innovative algorithms (mainly Numpy).Creation of a multi-disciplinary engineering team (electronics, FPGA, DSP and Android system/apps).Technical authority and technical lead for the engineering team.Design and code reviews.Mentoring of junior engineers.
Cambridge, United Kingdom
Technical authority for FPGA and digital hardware development.New technologies and processes champion (i.e. adoption of SystemVerilog/UVM, Altium integration with company database, continuous integration for FPGA development, etc).Interim project manager (multiple projects, team size up to 6 engineers).FPGA design and verification (Xilinx and Lattice)..
Systems engineer and WBE responsible at Selex Galileo.
Systems engineer. In charge of various flight simulator WBEs. Defining and designing sub-systems and architecture for simulation system either in the concept or the development phase. Leading the technical and engineering activities required by the specific role. Reviewing the sub-system designs and current architecture choices, documenting the agreed.
Project leader for: a vehicle tracking and safety system, a ticket vending machine, home automation project. Development of system level designs from customer proposals. Project reviews. System qualification prior to production sign off. Systems design (mechanical, electronic, electrical, software). 2D and 3D mechanical design. Cabling harness design..
FPGA design with VHDL and Verilog (Xilinx Virtex4 and Lattice XP2). Embedded system design with PPC, ARM, AVR32 and x86 processor. Linux device driver programming. Bootloader hacking (u-boot). Schematic entry. SoC design. Real-time video application with AVR32 (http://www.dave.eu/index.php?page=3#CS1). Student mentoring (BSEE thesis of M. Geromin “Embedded.
Cluster installation, hardware configuration, software installation and customization. Tuning, testing and benchmarking. Customer support (remote and on site). Diskless and live cd solutions development. Consultant coordination. PLC-based automation system design. Rack power distribution unit design. One cluster rated at Top500.
FPGA remote update systems design. Digital design with VHDL and Quartus II from Altera. Altera Nios II peripheral design and its device driver. PCI-X core interfacing. C and Perl programming. USB interfacing with FTDI devices. Linux low level application developing.
Dissertation titled "Remote update systems for FPGA in High Performance Computing applications"
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Matteo Vit works for Starware Design Limited.
Matteo Vit is listed as Director / Principal Design Engineer at Starware Design at Starware Design Limited.
AeroLeads has found 1 work email signal at @starwaredesign.com for Matteo Vit at Starware Design Limited.
Matteo Vit is based in Greater Cambridge Area, United Kingdom, United Kingdom while working with Starware Design Limited.
Matteo Vit has worked for Starware Design Limited, Cambridge Touch Technologies Ltd, Amantys Ltd, Altran Italia S.P.A., and Selex Galileo.
You can use AeroLeads to view verified contact signals for Matteo Vit at Starware Design Limited, including work email, phone, and LinkedIn data when available.
Matteo Vit holds Master Of Science (Msc), Electronic Engineering from Università Degli Studi Di Trieste.
Matteo Vit is listed with skills including Embedded Systems, Fpga, Vhdl, Electronics, Arm, C, Device Drivers, and Embedded Linux.
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