Matthew Plavcan Email & Phone Number

Portland, OR, US

Portland, Oregon Area

• Enterprise transformation and technical practices adoption for software and hardware.Building coaches and development teams.Improve your organization's capabilities:
• Continuous Delivery
• Incremental / Iterative Features
• Test-Driven Development
• Refactoring
• Continuous Integration

Portland, Oregon Area

• Improving commercial, law enforcement, and military driver training through virtual reality simulation.
• Product roadmap
• Customer relations
• Team culture and hiring
• Technology readiness
• Product architecture

Portland, Oregon Area

Refreshed perspective, relaxed, retooled.

Portland, Oregon Area

• Created Intel Innovation Hub: A place inside Intel where employees imagine, innovate, and create without the limits that the bureaucracy of a large company place on employees; A showcase of Intel technology providing.
• Mentored individuals in use of Arduino devices, 3D-printing, laser-cutters, and general electronics
• Supported hackathon events outside the Hub and Intel, including Stanford's Treehacks
• Maintained and managed computer and Maker equipment in Hub

Portland, Oregon Area

• Enterprise coach responsible for guiding software and hardware development organizations to launch and sustain transformations through Agile, Lean techniques
• Instructed and promoted teams adopting XP software practices: Test-Driven Development, Refactoring, Source Control, Continuous Integration, Continuous Delivery
• Mentored senior developers in behavioral aspects of software development
• Developed and deployed company-wide Coderetreat and Code Dojo program for software skill practice; Trained event facilitators
• Organized and led cross-company community of practice for software skill development (Software Academy)

Portland, Oregon Area

• Investigation in new technologies and methods on lead microprocessor products
• Developed bug-filing methodology and tool, and deployed with training to entire product design team (originally ~300 engineers, process and material is still in use)

Penang, Malaysia

• Pre-Silicon verification of lead microprocessor products: Haswell/Broadwell (Core i7)
• Mentored team of engineers on micro-architecture and testing methods
• Scrum Master for Agile adoption
• Represented project design organization in cross-company panel for convergence of bug-filing methodology
• Chaired cross-company methodology forum for 2 months during lead's sabbatical
• Wrote unit test and mocking framework for Specman/e from scratch, deployed to team

Portland, Oregon Area

• Test environment owner / software developer for pre-silicon verification of lead microprocessor product: Haswell (Core i7)
• Maintained and extended memory "cluster" (multi-unit) simulation test environment, supporting team of ~15 design/verification engineers
• Ported code base (150k+ lines) from team with different methodology, refactored code to promote ease of maintainability.
• Explored technical readiness verification options for upcoming product development

Portland, Oregon Area

• Software developer / Hardware logic verification for lead microprocessor products: Nehalem/Westmere (Core i7)
• Root-caused and guided closure of post-silicon logic failures gating product release
• Identified significant gap in architectural specification, created corporate standard used by all microprocessor product teams
• Supported and enhanced memory execution test environment for team of ~10 engineers
• Supported and enhanced bus-functional model of Common Systems Interface for team of ~15 engineers

Portland, Oregon Area

• Software developer / logic verification for memory execution cluster in lead microprocessor product: Nehalem (Core i7)
• Architect and lead developer for a new test generator used by ~10 engineers
• Created and published an extensive methodology for root-causing, filing, tracking, and closing bugs for entire organization. Foundation still used and referenced as of 2018
• Extended the simulation test environment for the "memory execution" cluster, covered for owner during their sabbatical

Portland, Oregon Area

• Verification engineer for pre/post-silicon in multiple functional units / debugging of full-chip failures in lead microprocessor products: Willamette/Northwood/Prescott (Pentium 4)
• Led logic verification of critical late release-gating memory-ordering post-silicon bug
• Debugged slow timing paths in using Laser Voltage Probing of silicon
• Trained design team to create x86-assembly based tests for silicon structural testers
• Created coverage analysis for tests of silicon signal noise conditions
• Extended common memory "cluster" random testing tool

Portland, Oregon Area

• Pre-silicon Logic verification engineer of two functional units for lead microprocessor products: Willamette/Northwood (Pentium 4)
• Ran random testing and coverage-based analysis of instruction decode and trace cache logic
• Enhanced testing environment accuracy, resulting in the discovery of several difficult-to-find bugs
• Drove adoption of knowledge and methods sharing among team
• Enhanced coverage automation tools to ease strain on testing team
• Built software testing libraries to promote common test base abstraction across developers

Urbana-Champaign, Illinois Area

• Class Instructor, ECE 291 (Computer Engineering II)Providing an introduction to computer architecture and low-level programming to engineering students.
• Presented course lecture material on Intel x86 assembly-language and PC architecture
• Wrote exams and lab programming exercises
• Supervised Teaching Assistants

Urbana-Champaign, Illinois Area

• Engineering Teaching Assistant, ECE291 (Computer Engineering II)Supporting engineering students in learning computer architecture and low-level programming concepts.
• Authored new course material for: coding techniques, abstracting low-level hardware control
• Supported students for lab programming exercises
• Graded exams and labs

Houston, Texas Area

• Intern with Performance Laptop Expansion group
• Debugged logic and timing design of laptop docking station PCBs.
• Created software for programming unique ID in memory module production line.
• Evaluated high-performance networking options for future expansion accessories.

Houston, Texas Area

• Intern with Performance Laptop Expansion group
• Learned memory controller protocols for Synchronous DRAM
• Drove SO-DIMM as JEDEC standar for laptop memory expansions
• Designed and constructed hot-pluggable laptop drive bay (non-assigned project)