Matthew Plavcan Email and Phone Number
atlanta, georgia, united states
Matthew Plavcan's Location
Portland, Oregon, United States, United States
Matthew Plavcan's Contact Details
Matthew Plavcan work email
- Valid
- Valid
Matthew Plavcan personal email
n/a
About Matthew Plavcan
Matthew Plavcan is a Engineering Technical Coach, Software / Hardware Technical Lead at Nerd/Noir. He possess expertise in debugging, microprocessors, computer architecture, process improvement, software development and 22 more skills. He is proficient in Japanese and Spanish.
Matthew Plavcan's Current Company Details
Nerd/Noir
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Engineering Technical Coach, Software / Hardware Technical Lead
atlanta, georgia, united states
- Website:
- nerdnoir.com
- Employees:
- 3
Matthew Plavcan Work Experience Details
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Senior CoachNerd/Noir Feb 2023 - Present
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Engineering Technical CoachTacit Focus, Llc Mar 2017 - PresentPortland, Oregon AreaEnterprise transformation and technical practices adoption for software and hardware.Building coaches and development teams.Improve your organization's capabilities:• Continuous Delivery• Incremental / Iterative Features• Test-Driven Development• Refactoring• Continuous Integration• Process ImprovementAre you looking for more than an individual to address your company's needs?I work with the following organizations to assemble a coaching team to meet your needs: - Nerd/Noir - Cprime - Industrial Logic - Odd-e -
Chief Technology OfficerVr Motion Sep 2017 - Jun 2022Portland, Oregon AreaImproving commercial, law enforcement, and military driver training through virtual reality simulation.• Product roadmap • Customer relations• Team culture and hiring• Technology readiness• Product architecture• Software/hardware integration• Product implementation -
Personal Sabbatical(None) Aug 2016 - Feb 2017Portland, Oregon AreaRefreshed perspective, relaxed, retooled.
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Intel Innovation Hub StewardIntel Corporation Jan 2016 - Jul 2016Portland, Oregon AreaCreated Intel Innovation Hub: A place inside Intel where employees imagine, innovate, and create without the limits that the bureaucracy of a large company place on employees; A showcase of Intel technology providing social good to the outside world• Mentored individuals in use of Arduino devices, 3D-printing, laser-cutters, and general electronics• Supported hackathon events outside the Hub and Intel, including Stanford's Treehacks• Maintained and managed computer and Maker equipment in Hub -
Enterprise Technical Practices CoachIntel Corporation Dec 2012 - Jul 2016Portland, Oregon AreaEnterprise coach responsible for guiding software and hardware development organizations to launch and sustain transformations through Agile, Lean techniques• Instructed and promoted teams adopting XP software practices: Test-Driven Development, Refactoring, Source Control, Continuous Integration, Continuous Delivery• Mentored senior developers in behavioral aspects of software development• Developed and deployed company-wide Coderetreat and Code Dojo program for software skill practice; Trained event facilitators• Organized and led cross-company community of practice for software skill development (Software Academy)
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Staff Component Design EngineerIntel Corporation Jul 2012 - Nov 2012Portland, Oregon AreaInvestigation in new technologies and methods on lead microprocessor products• Developed bug-filing methodology and tool, and deployed with training to entire product design team (originally ~300 engineers, process and material is still in use)
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Staff Component Design EngineerIntel Corporation Jul 2011 - Jun 2012Penang, MalaysiaPre-Silicon verification of lead microprocessor products: Haswell/Broadwell (Core i7)• Mentored team of engineers on micro-architecture and testing methods• Scrum Master for Agile adoption• Represented project design organization in cross-company panel for convergence of bug-filing methodology• Chaired cross-company methodology forum for 2 months during lead's sabbatical• Wrote unit test and mocking framework for Specman/e from scratch, deployed to team
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Senior Component Design EngineerIntel Corporation Jan 2009 - Jun 2011Portland, Oregon AreaTest environment owner / software developer for pre-silicon verification of lead microprocessor product: Haswell (Core i7)• Maintained and extended memory "cluster" (multi-unit) simulation test environment, supporting team of ~15 design/verification engineers• Ported code base (150k+ lines) from team with different methodology, refactored code to promote ease of maintainability.• Explored technical readiness verification options for upcoming product development
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Senior Component Design EngineerIntel Corporation Jan 2007 - Dec 2008Portland, Oregon AreaSoftware developer / Hardware logic verification for lead microprocessor products: Nehalem/Westmere (Core i7)• Root-caused and guided closure of post-silicon logic failures gating product release• Identified significant gap in architectural specification, created corporate standard used by all microprocessor product teams• Supported and enhanced memory execution test environment for team of ~10 engineers• Supported and enhanced bus-functional model of Common Systems Interface for team of ~15 engineers
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Senior Component Design EngineerIntel Corporation Nov 2004 - Dec 2006Portland, Oregon AreaSoftware developer / logic verification for memory execution cluster in lead microprocessor product: Nehalem (Core i7)• Architect and lead developer for a new test generator used by ~10 engineers• Created and published an extensive methodology for root-causing, filing, tracking, and closing bugs for entire organization. Foundation still used and referenced as of 2018• Extended the simulation test environment for the "memory execution" cluster, covered for owner during their sabbatical
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Senior Hardware Validation EngineerIntel Corporation Mar 2000 - Nov 2004Portland, Oregon AreaVerification engineer for pre/post-silicon in multiple functional units / debugging of full-chip failures in lead microprocessor products: Willamette/Northwood/Prescott (Pentium 4)• Led logic verification of critical late release-gating memory-ordering post-silicon bug• Debugged slow timing paths in using Laser Voltage Probing of silicon• Trained design team to create x86-assembly based tests for silicon structural testers• Created coverage analysis for tests of silicon signal noise conditions• Extended common memory "cluster" random testing tool• Prototyped pseudo-simulation of hardware conditions to create more effective fullchip tests
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Pre-Silicon Hardware Validation EngineerIntel Corporation Aug 1997 - Mar 2000Portland, Oregon AreaPre-silicon Logic verification engineer of two functional units for lead microprocessor products: Willamette/Northwood (Pentium 4)• Ran random testing and coverage-based analysis of instruction decode and trace cache logic• Enhanced testing environment accuracy, resulting in the discovery of several difficult-to-find bugs• Drove adoption of knowledge and methods sharing among team• Enhanced coverage automation tools to ease strain on testing team• Built software testing libraries to promote common test base abstraction across developers
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InstructorUniversity Of Illinois At Urbana-Champaign Jun 1997 - Aug 1997Urbana-Champaign, Illinois AreaClass Instructor, ECE 291 (Computer Engineering II)Providing an introduction to computer architecture and low-level programming to engineering students.• Presented course lecture material on Intel x86 assembly-language and PC architecture• Wrote exams and lab programming exercises• Supervised Teaching Assistants -
Teaching AssistantUniversity Of Illinois At Urbana-Champaign Jan 1996 - May 1997Urbana-Champaign, Illinois AreaEngineering Teaching Assistant, ECE291 (Computer Engineering II)Supporting engineering students in learning computer architecture and low-level programming concepts.• Authored new course material for: coding techniques, abstracting low-level hardware control• Supported students for lab programming exercises• Graded exams and labs
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Electrical Engineering InternCompaq Computer Corporation Jun 1996 - Aug 1996Houston, Texas AreaIntern with Performance Laptop Expansion group• Debugged logic and timing design of laptop docking station PCBs.• Created software for programming unique ID in memory module production line.• Evaluated high-performance networking options for future expansion accessories.
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Electrical Engineering InternCompaq Computer Corporation Jun 1995 - Aug 1995Houston, Texas AreaIntern with Performance Laptop Expansion group• Learned memory controller protocols for Synchronous DRAM• Drove SO-DIMM as JEDEC standar for laptop memory expansions• Designed and constructed hot-pluggable laptop drive bay (non-assigned project)
Matthew Plavcan Skills
Debugging
Microprocessors
Computer Architecture
Process Improvement
Software Development
Embedded Systems
Perl
Verilog
Semiconductors
Asic
Soc
Agile Methodologies
Test Driven Development
Continuous Integration
Extreme Programming
C
C++
Specman
Programming
Testing
Kanban
Scrum
Unity3d
High Performance Driving
Judo
Driver Training
Auto Racing
Matthew Plavcan Education Details
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Bachelor Of Science (B.S.)
Frequently Asked Questions about Matthew Plavcan
What company does Matthew Plavcan work for?
Matthew Plavcan works for Nerd/noir
What is Matthew Plavcan's role at the current company?
Matthew Plavcan's current role is Engineering Technical Coach, Software / Hardware Technical Lead.
What is Matthew Plavcan's email address?
Matthew Plavcan's email address is mp****@****orp.com
What schools did Matthew Plavcan attend?
Matthew Plavcan attended University Of Illinois At Urbana-Champaign.
What skills is Matthew Plavcan known for?
Matthew Plavcan has skills like Debugging, Microprocessors, Computer Architecture, Process Improvement, Software Development, Embedded Systems, Perl, Verilog, Semiconductors, Asic, Soc, Agile Methodologies.
Who are Matthew Plavcan's colleagues?
Matthew Plavcan's colleagues are Ed Tilford, Alexandra West.
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