• Developed, validated, and deployed Calibre DRC to implement DFM guideline checks for 90, 65, 55 and 45 nm CMOS technologies. Achieved 100% guideline checking on library and custom cells.• Developed Calibre SVRF decks to create Double Patterning gate level masks for 130 nm. Successfully implemented in volume manufacturing. • Designed automatic data flow and infrastructure for Calibre rule decks.• Collaborated with SoC design engineers and PDK layout team to develop, validate and deploy Calibre DRC rule decks for DFM.• Collaborated with product design groups to improve via redundancy and reduce total chip critical area using Calibre SVRF.• Created Calibre DFM scripts for statistical analysis of critical area and via redundancy in full-chip designs. • Applied knowledge of gate lithography and mask OPC to create DFM guidelines that reduce gate CD variation.• Collaborated with wafer process engineers to identify layout configurations that were problematic for manufacturing, resulting in DFM guidelines that supplemented the design rules. • Created litho simulation scripts using foundry DDK to check full chip metallization for areas of poor lithographic process margin. • Developed and supported Calibre SVRF scripts that automatically increased post-tapeout via redundancy.