2010-2021, Program Manager in Packaging R&D; Wafer-level package, incl. 3DIC (SoIC), fan-in (WLCSP), fan-out (InFO), CoWoS and Flip Chip CPI. Extending to module/system-level package, e.g. SIP or AIP.The role is process integration program manager. The scope is from chip-package-system assessment, cost estimation, TV design, Si BEOL, bump, assembly, FT process to reliability assessment, customer engagement, product qual and ramp-up.Manage a team with 7 members.2007-2010: Technical Manager in Packaging Q&R; Covering line quality, component-, board- & system-level reliability.3 ECTC papers (1st author, speaker).> 50 patents.TSMC innovation award, VP most business impact award, golden trade secret award.

As a project leader to coordinate multi-cultural packaging team.Responsible for package definition & development of new products from communication BUs. The scope starts from package concept to work with BU chip/system designers for package solution selection, and then act as package project leader to execute package project with assembly house (in-house or subcons) till qualification & production ramp-up. The package types include QFP, BGA, MCM, flip chip and VQFN etc.Another job during this period is subcon (ASE) management, including schedule control, technical problem solving, reliability issue and customer return support etc.

Responsible for package RD. 4 major RD projects during this period, Mini BGA, Green PBGA/Mini BGA, PBGA with passive components (SMT), Stacked CSP (MCP), with hands-on assembly process experiences, new process stage build-up, qualification & failureanalysis, and FEMA & 8D report etc.Also experienced in SMT outsourcing management, SMT line build-up, thermal lab build-up, package BOM & cost estimation & QS9000 certification.Hsinchu science park outstanding labor award. (2004)