Max Baker Email & Phone Number

Santa Clara, Ca, Us

“NVIDIA is reshaping the future of computing. We’ve built a culture where people can do their life's work. We are a learning machine. The mission is boss. Everyone has a voice.” — Jensen Huang

Santa Clara, Ca, Us

Delivering new composable architectures through the development of hardware and software designed to optimize system performance.

Mountain View, California, Us

Chip lead for a cutting edge System-on-Chip (SoC) at the heart of Waymo's next generation driving platform.- Full-chip floorplan owner- Cost analysis for SoC including NRE, Part Price, TCO, System BOM - Lead for ASIC Vendor evaluation and selection- IP Vendor selection- Chip architecture for "uncore" features- Team lead for full-chip / physical design workstream

Mountain View, California, Us

As one of the first employees at a startup, I've helped define the product, bootstrap the engineering organization, set best practices, and grow the team. With a very lean team we created a 26B transistor 14nm ASIC capable of 1 peta-Op per second that went to production with A0 silicon. I managed the Systems and ASIC Logic Design teams, and was lead Systems Architect.• Lead of system architecture and roadmap design for machine learning accelerator products. • Evaluate Power, Performance, and Area (PPA) trade off analysis for our next-generation product family. Guide team to quickly reduce choices and make architectural decisions.• Manage vendor relations including ASIC vendor, process node, IP, and tool chain evaluation and selection. • Manage vendor relations for Systems Group : PCB Design, Electronics Manufacturing Services (EMS), thermal and mechanical. • Socket, SERDES, and ASIC Package owner including technology selection, design specification, vendor selection, and oversight.• SOC Architect for the “plumbing”: Serdes, Clocks, Resets, CSRs, PDN, SPI, and I2C for High-Performance Computing (HPC) / Machine Learning (ML) products. • Create and own ASIC datasheet. • Code generation flows in Python leveraged by design team.• Security lead at Groq. Architected and implemented all hardware security features on ASIC including secure boot and program encryption features.• As founding Systems team member, I oversaw the definition and creation of our first PCBA, including an 18-layer low-loss material PCB for a high-power PCIe Gen 4 CEM accelerator card. The card was production ready on the first revision with no blue wires. Grew team to five members.• Personally deployed two state-of-the-art semiconductor R&D labs to allow rapid V&C of first silicon and PCBAs. Lead all site and equipment selections, facility construction, electrical, and datacenter requirements.

San Francisco, Ca, Us

* Owner of DPARC security IP product line consisting of side-channel protected cryptographic cores. Including roadmap development, micro-architecture specification, customer pre-sales and design team direction. Grew and managed a design team of crypto specialists across 3 geographies.* Technical lead of the ASIC design team at Cryptography Research in charge of design methodology and technical growth. * R&D of hardware security cores, side-channel countermeasures and true random number generators focusing on ASIC and FPGA-compatible Verilog

San Francisco, Ca, Us

* Roll-out of new security IP product line of side-channel protected cryptographic cores. Customer pre- and post-sales support for high volume system-on-chip (SOC) designs in deep-submicron planar and FinFET CMOS* CAD design of design flows for ASIC group in Perl, Python, TCL, and Make, including Synopsys DesignCompiler, PrimeTime. Xilinx Vivado, and Cadence Conformal* Lead of design, manufacture, and characterization of FPGA-based emulation platform including PCB Specification, microarchitecture, and RTL design. Used by internal design groups and customers for side-channel evaluation* Specification and design of ASIC testchip platform for side-channel characterization of IP cores, from architecture through RTL design, and ultimately first silicon bring-up* Differential power analysis (DPA) of hardware cryptographic cores

Santa Clara, Ca, Us

Hardware Architect of DesignInsight, a novel chip-level debug and in-system monitoring platform for SpaceTime 3D architecture, called a "game changer" by EE Times. DesignInsight provided full observability at speed, in real-time, without changing the existing design. You select the signals to debug, and they are routed over dedicated resources to dedicated trigger and trace buffer blocks, without disturbing the existing design, or even requiring a reset* Sole developer of 0.5M-gate ASIC block in Verilog targeting 2.2GHz on Intel 22nm FinFET Process. From R&D, HW Spec Creation, RTL design, Embedded Custom IP integration, and Schematic Design through Verification and Physical Design on to tapeout. Create and drive verification and physical design teams for this system-level feature* Create, deploy and maintain Synthesis flow for whole hardware group using Design Compiler, Conformal and PrimeTime using Perl, Make and TCL

San Jose, Ca, Us

* VLSI and Verilog Digital Design on flagship Virtex6 and Virtex7 families on SRAM and Chip Configuration blocks* Owner of family-wide porting effort of existing VLSI schematic transistor designs to RTL-based designs in Verilog including equivalency checking and synthesis analysis* Owner SRAM (BRAM) MBIST & FIFO features

San Jose, Ca, Us

* Microarchitecture to RTL to GDS of Virtex5 & Virtex6 Configuration Controller in UMC 65nm and UMC 40nm. Design, Synthesis, STA, LEC, and Verification * Owner of Bitstream Security Blocks (AES256, SHA256)* Test bench and test plan creation. Verification at Verilog and Spice levels. Full-chip power simulations* 1st-silicon bring-up, including characterization plan, vector creation, and yield recovery* Part of a small team to create the radiation-hardened Virtex-5QV "SIRF" FPGA. Creation of flows and tools to accomplish rad-hard digital design in IBM 65nm. Bitstream Security and rad-hard “beam” testing* Secure DFT design* Designer of JTAG, SPI, GPIO, E-Fuse, Configuration, Single-Event Upset (SEU), Global Signal Blocks

San Jose, Ca, Us

* First-silicon validation of Virtex-4 (90nm) Configuration Block including full-chip reset, NOR flash integration, and JTAG* PCB schematic design, PCB layout review and board bring-up * Jitter characterization of “Pocket Function Generator” lab frequency generator usingLeCroy DSO

New York, Ny, Us

* System Administrator and CAD Administrator for IC Design Labs. Solaris and Linux deployments. Synopsys, Cadence, Xilinx tool chains

Santa Cruz, Ca, Us

* Creator of Netdisco (see below)* Other tool development related to Linux CatOS, Cisco IOS, Perl, SQL, FreeBSD, SNMP and Visualization

Back-end Perl programming for Toyota.com.

* MCSE NT 3.51* Novell Netware

Masters Science, Electrical Engineering

Bs, Computer Engineering

Linguistics