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@elastics.cloud
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3 phones found area 641 and 515
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Max Baker is listed as Principal Platform Architect at NVIDIA at NVIDIA, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at elastics.cloud, phone signal with area code 641, 515, and a matched LinkedIn profile for Max Baker.
Max Baker previously worked as Principal Platform Architect at Nvidia and Principal Engineer (Acquired by Broadcom) at Elastics.Cloud, Inc.. Max Baker holds Masters Science, Electrical Engineering from Columbia University.
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AeroLeads found 1 current-domain work email signal for Max Baker. Compare company email patterns before reaching out.
I am a System and ASIC architect specializing in the creation of strange chips. I focus on system- and product-level design problems. Previous projects have included novel machine learning accelerators, radiation-hardening, time-division multiplexed datapaths, design of FPGAs, and side-channel protected cryptographic cores. I have been involved in all phases of design from specification, design, verification, physical implementation, first silicon, packaging, PCBA design, and volume production. I am an expert in RTL-based design, the Verilog language, and ASIC toolchains. I enjoy the development and rollout of design flows and infrastructure for design groups, especially scripting and automation. This is complemented by past roles working as a software engineer, verification engineer, and in IT.
Listed skills include Asic, Verilog, Xilinx, Fpga, and 10 others.
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A career timeline built from the work history available for this profile.
Santa Clara, CA, US
“NVIDIA is reshaping the future of computing. We’ve built a culture where people can do their life's work. We are a learning machine. The mission is boss. Everyone has a voice.” — Jensen Huang
Santa Clara, CA, US
Delivering new composable architectures through the development of hardware and software designed to optimize system performance.
Mountain View, California, US
Chip lead for a cutting edge System-on-Chip (SoC) at the heart of Waymo's next generation driving platform.- Full-chip floorplan owner- Cost analysis for SoC including NRE, Part Price, TCO, System BOM - Lead for ASIC Vendor evaluation and selection- IP Vendor selection- Chip architecture for "uncore" features- Team lead for full-chip / physical design.
Mountain View, California, US
San Francisco, CA, US
* Owner of DPARC security IP product line consisting of side-channel protected cryptographic cores. Including roadmap development, micro-architecture specification, customer pre-sales and design team direction. Grew and managed a design team of crypto specialists across 3 geographies.* Technical lead of the ASIC design team at Cryptography Research in.
San Francisco, CA, US
* Roll-out of new security IP product line of side-channel protected cryptographic cores. Customer pre- and post-sales support for high volume system-on-chip (SOC) designs in deep-submicron planar and FinFET CMOS* CAD design of design flows for ASIC group in Perl, Python, TCL, and Make, including Synopsys DesignCompiler, PrimeTime. Xilinx Vivado, and.
Santa Clara, CA, US
Hardware Architect of DesignInsight, a novel chip-level debug and in-system monitoring platform for SpaceTime 3D architecture, called a "game changer" by EE Times. DesignInsight provided full observability at speed, in real-time, without changing the existing design. You select the signals to debug, and they are routed over dedicated resources to dedicated.
San Jose, CA, US
* VLSI and Verilog Digital Design on flagship Virtex6 and Virtex7 families on SRAM and Chip Configuration blocks* Owner of family-wide porting effort of existing VLSI schematic transistor designs to RTL-based designs in Verilog including equivalency checking and synthesis analysis* Owner SRAM (BRAM) MBIST & FIFO features
San Jose, CA, US
* Microarchitecture to RTL to GDS of Virtex5 & Virtex6 Configuration Controller in UMC 65nm and UMC 40nm. Design, Synthesis, STA, LEC, and Verification * Owner of Bitstream Security Blocks (AES256, SHA256)* Test bench and test plan creation. Verification at Verilog and Spice levels. Full-chip power simulations* 1st-silicon bring-up, including.
San Jose, CA, US
* First-silicon validation of Virtex-4 (90nm) Configuration Block including full-chip reset, NOR flash integration, and JTAG* PCB schematic design, PCB layout review and board bring-up * Jitter characterization of “Pocket Function Generator” lab frequency generator usingLeCroy DSO
New York, NY, US
* System Administrator and CAD Administrator for IC Design Labs. Solaris and Linux deployments. Synopsys, Cadence, Xilinx tool chains
Santa Cruz, CA, US
* Creator of Netdisco (see below)* Other tool development related to Linux CatOS, Cisco IOS, Perl, SQL, FreeBSD, SNMP and Visualization
Back-end Perl programming for Toyota.com.
* MCSE NT 3.51* Novell Netware
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Jim Jernigan
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Redmond, Washington, United States, United States
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Kotaro Hata
Colleague at Nvidia
Yokohama, Kanagawa, Japan, Japan
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Toby Chen
Colleague at Nvidia
San Francisco Bay Area, United States, United States
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JK
Junghyun Kim
Colleague at Nvidia
San Jose, California, United States, United States
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손
손종우
Colleague at Nvidia
South Korea, Korea, Republic Of
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AB
Anjuman Banu
Colleague at Nvidia
Davangere, Karnataka, India, India
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QT
Quan Tran
Colleague at Nvidia
United States, United States
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NP
Naman Parashar
Colleague at Nvidia
San Francisco Bay Area, United States, United States
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SS
Sujith Solleti
Colleague at Nvidia
Hyderabad, Telangana, India, India
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SR
Shivanand Ramesh Pujari
Colleague at Nvidia
San Francisco Bay Area, United States, United States
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Quick answers generated from the profile data available on this page.
Max Baker works for NVIDIA.
Max Baker is listed as Principal Platform Architect at NVIDIA at NVIDIA.
AeroLeads has found 1 work email signal at @elastics.cloud for Max Baker at NVIDIA.
AeroLeads has found 3 phone signal(s) with area code 641, 515 for Max Baker at NVIDIA.
Max Baker is based in San Francisco Bay Area, United States, United States while working with NVIDIA.
Max Baker has worked for Nvidia, Elastics.Cloud, Inc., Waymo, Groq, and Cryptography Research.
Max Baker's colleagues at NVIDIA include Jim Jernigan, Kotaro Hata, Toby Chen, Junghyun Kim, and 손종우.
You can use AeroLeads to view verified contact signals for Max Baker at NVIDIA, including work email, phone, and LinkedIn data when available.
Max Baker holds Masters Science, Electrical Engineering from Columbia University.
Max Baker is listed with skills including Asic, Verilog, Xilinx, Fpga, Rtl Design, Ic, Static Timing Analysis, and Integrated Circuit Design.
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