May W. Email & Phone Number

Creative & passionate self-starter with 8+ years hands on multiple foundry physical design experience implementing ASIC/SOC design from specification to silicon for 20+ blocks in advanced nodes. Highlights of my expertise include, Achieve 20% power saving after applying low power techniques.  Slash 6% block area after optimizing P&R methodologies and layout.  Suggest design changes per P&R trial run to design team to fix timing.  Host WebEx P&R status meetings with India/Japan/China teams. Lead 6 engineers to deliver projects on tight schedule.(WD:3,Broadcom:3) Support a critical new block (that was not meeting timing) 2 weeks before tape out, achieved timing closure & delivered tape out on time. Develop RTL/netlist to GDS2 flow: synthesis, floor planning, place and route, CTS, RC extraction, STA, DFT scan chain reordering, timing sign off.

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  San José State University

  Electrical And Electronics Engineering