Cores performance modelling team• Working in AMD performance simulators for the zen family. Developing architectural changes and testing for IPC(instruction per cycle) changes.• Contributing in the modelling of an ML based DRAM model(using XGBoost ML models) which predicts the DRAM read and write latencies requested by the L3 cache, hence removing the traditional DRAM from the performance simulator.• This model alone reduces the simulator wallclock runtime by almost 50 percent.• Improved runtime performance of ML models by 5% and reduced memory footprint by 30% in specific suite• Have gained strong fundamentals in CPU and memory architecture like caches, prefetchers, advanced page replacement algorithms like RRIP, multi-core shared systems, inclusive/exclusive caches, and advanced architecture concepts.• Strong hold and understanding of performance simulators, running them on lsf, debugging, C++, python, linux.

Responsible for conducting academic,technical,co-curricular and social activities for students.

Responsible for programming electrical circuits required in projects as well as implementing the same.---> 1st position in Electric Solar Vehicle Championship