Led a smartphone software development team in leveraging AI and 3D pose estimation to assess and minimize fall risk and cognitive impairment in older adults, achieving performance up to 20 FPS on the device SoC.* Optimized a Deep Learning (DL) 3D pose model and extracted TensorFlow TFLite and Apple Model Package representations.* Engineered a scheduler in Swift to map separated model parts of TFLite and MLPackage to NE (NPU)/CPU/GPU processing nodes.* Leveraged ASW cloud services such as Cognito, DynamoDB, and S3.

Developing a self-supervised training framework tailored for transformer-based architectures in the realm of computer vision, with a focus on enhancing contextual understanding in 2/3-D pose estimation tasks.* Developed expertise in training discrete Variational Autoencoders (dVAEs) for the tokenization of human pose movements through the analysis of generated skeleton heatmaps.* Pre-trained transformer-based models, such as ViT and BERT-like architectures by leveraging the dVAE encoder for self-supervised pre-training of vision-based transformers. This comprehensive approach involved masking tokens and heatmap patches, enhancing the model's ability to grasp the contextual nuances of human anatomy.* Specialized in fine-tuning pre-trained models for tasks requiring detailed skeletal information, such as action classification, thereby optimizing model performance for specific applications.

Designed and implemented an end-to-end scalable, intelligent advanced video surveillance vision pipeline, achieving a system performance of 23 FPS for eight concurrent cameras at Full HD resolution.* Used PyTorch Multiprocessing Process and Queues to parallelize four deep learning models inference on multiple GPUs.* Leveraged the Flask module to construct a RESTful API that serves an ML model across different camera clients.* Improved re-ID accuracy and reduced inference time by employing mixed-precision training on large datasets, such as DukeMTC and CUHK03.

Designed and developed Agile Temporal Convolutional Neural Network (ATCN), a scalable deep learning model with adjustable hyper-parameters to enable time series analysis for resource-constrained edge systems.* Implemented in C/C++, the solution consumed only 49% of the 320KB RAM and 15% of the 1MB flash memory available on a Cortex-M7 microcontroller.* Used data augmentation techniques, such as jittering, magnitude warping, window warping, and scaling, to enhance model robustness on the UCR 2018 dataset.Implemented HW/CW co-design for application-specific architectures, accelerating EfficientNet and MobileNetV2 inference on Xilinx embedded and cloud FPGAs. Achieved an improvement of up to 8.6x FPS/W.* ML model optimization such as quantization (4-bit), layers fusion, pruning, and activation approximation.* Hardware-level optimization includes pipelining, window buffering, etc.Invented a customized multi-head attention Temporal Convolutions Network (TCN) for efficiently and precisely predicting highway vehicle trajectories for highway and self-driving car safety applications. * Redesigned dilated TCN with separable depth-wise convolutional neural network to reduce the model size and complexity by approximately 33.16% compared to LSTM-based approaches.Designed a recurrent deep learning solution for real-time edge processing in reliability modeling of Si-MOSFET power electronics converters. * Designed stacked LSTM networks for time series analysis.* Utilized the NASA dataset for training and validation to enhance the final accuracy.Designed a behavioral simulator for cache and various branch predictors (G-Share, one-level, two-level global, two-level local). Also developed a tool for recognizing independent instructions in X86 and ARM assembly, enabling dependency graph extraction.* Utilized Python to develop the simulator, ensuring flexible module implementation.* The code processes logs of executed instructions obtained from Intel Pin tools.

Designed and verified modules for a satellite component providing internet access.* Design and verification of a generic True Dual-Port Memory for Microsemi RTG4 FPGA in Verilog.* Created a generic Bus Functional Model (BFM) of AXI Stream (AXIS) using Object-Oriented Programming (OOP) to accommodate different AXIS variations in SystemVerilog.