Md Basharat Ali Email and Phone Number
(408) 765-8080
Md Basharat Ali's Location
Hillsboro, Oregon, United States, United States
Md Basharat Ali's Contact Details
Md Basharat Ali work email
- Valid
- Valid
Md Basharat Ali personal email
n/a
About Md Basharat Ali
ASIC and SOC verification lead with around 15 yrs of experience.Have worked on ARM processors, Networking, telecommunication, verification of various SOC designs. Great ability to drive projects to completion, both technically and as a resource manager. Skilled in different VLSI related languages (VHDL, Verilog, Sytem verilog, OVM, VMM), scripting (perl, ocaml, python,shell,etc). and different tools (VCS, Modelsim,etc).
Md Basharat Ali Work Experience Details
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Verification LeadIntel Corporation Oct 2016 - PresentSanta Clara, California, Us -
Verification ConsultantWipro Limited Dec 2014 - Aug 2016Bangalore, Karnataka, InVerification of SOC, with integration of various custom blocks. A Configurable SOC architecture , for a semi conductor lead company. -
Verification ManagerWipro Limited Jun 2000 - Aug 2016Bangalore, Karnataka, InLead a verification team and drive the project to closure on verification aspects. Help the team in technical issues both with coding and debugging of the design. Plan verification activities, assign resources, and track the progress of the project. Report the status on the project to the client.
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Technical ConsultantWipro Limited Nov 2013 - Nov 2014Bangalore, Karnataka, InVerification of a complex engine block, in UVM methodology from scratch. Development of test plan, coding of test bench, test cases, regression, bug tracking, reviews, profiling, coverage, etc. Complete randomization of environment, including uvm register package.
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Verification ManagerWipro Limited Nov 2009 - Aug 2010Bangalore, Karnataka, InThe project was for functional verification of a complex architecture to support dataflow between different interfaces which includes USB (HUB, Host, Endpoint), SD card. Its a MIPS based system, with the SOC having support for differnt securities. Responsibilities: To make the verification strategy, verification plan, Regression scripts, Project Management, Test bench Buildup, Debugging of the design, C based programming of test cases.
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Verification LeadWipro Limited Sep 2009 - Oct 2009Bangalore, Karnataka, InThe project was to validate the VCS tool from Synopsys Inc. Responsibilities: To make the validation plan, run different designs on vcs tool, and make the existing test cases pass in the designs, using the new debug features of VCS.
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Verification LeadWipro Limited Mar 2008 - Apr 2008Bangalore, Karnataka, InThe Project was for functional verification of USB and it’s integration into an ASIC. The ASIC had a Synopsys USB OTG Core. The work revolved around testing the USB connectivity by doing different transfers, and USB protocols, there by verifying the functionality, and targeting the different memories in the ASIC. Responsibilities: Complete Ownership in verification of USB connectivity, and functional verification of the ASIC with USB fuctionality. C based programming for USB transfers. Test plan, testcases, coverage, etc. Leading a team to guide their areas of work in verification of this ASIC.
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Project LeadWipro Limited Mar 2008 - Apr 2008Bangalore, Karnataka, InProject was to design and develop the verification IP model of PCIe. Responsible as a Project Lead was to train the team on PCIe, system verilog and come up with the architecture for VIP development.
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Senior Verification EngineerWipro Limited Jul 2007 - Feb 2008Bangalore, Karnataka, InThe project was for functional verification of USB and PCIe interface modules. The SOC had USB and PCIe IP-Core modules, and was developing interfaces to these cores.Responsibilities: To make module level testbench environment for USB and PCIe interface modules. The Interface modules would be the bridge between USB/PCIe and the SOC. Make the test plan, write testbench components using Denali verification models, write testcases, and generate coverage reports, for both module level and system level environments.
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Senior Verification EngineerWipro Limited Dec 2006 - Jun 2007Bangalore, Karnataka, InThe project was to execute benchmarks on Cortex A8 model, and tweak the cycle wait states, with numbers from RTL.
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Senior Verification EngineerWipro Limited Apr 2004 - Nov 2006Bangalore, Karnataka, InThe project was to model the Cortex A8 processor, and use it as the golden reference model for verification. Responsibilities: was involved in modeling the complete Cortex A8 processor, with instruction set encoding (ARM, Thumb, Thumb-2, and later on support Neon instructions), Memory Manangement Module (VA to PA, security checks, L1-I and D Caches), Trustzone features, CoProcessor Module.Debugged the Trustzone suite of Assembly test cases, and supported the ISS (Instruction set simulator).
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Senior Verification EngineerWipro Limited Oct 2003 - Mar 2004Bangalore, Karnataka, InThe Superscalar, Dual issue ARM V7 Architecture based core is used for a Real time embedded application. Proect was to Support Darwin tool, to generate the controlled random test cases for Tiger processor. Involved in the Darwin team, which developed the Darwin tool to generate controlled random test case to test the processor. Involved in generating the combination of Functional points to generate the hit/miss matrix, based on which the test case worthiness would be decided.
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Senior Verification EngineerWipro Limited Mar 2003 - Sep 2003Bangalore, Karnataka, InThe Project was to develop clock accurate model of the three FPGAs supported for the PON architecture. The system models developed are used as golden reference in the verification environment. The system environment (involving only the system models) was to be used for study and analysis. The verification was done using Vera where the System-models were integrated with RTL written in Verilog, and test cases in Vera. Responsibility : Architecting the system models hierarchy and integration. Design and Development of MAC layer. Integration of models with the RTL environment for three FPGAs. Platform development for system Co-verification. Generation of system reports for analysis. Verification using Test cases written in Vera.
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Verification EngineerWipro Limited Nov 2002 - Feb 2003Bangalore, Karnataka, InThe project was to develop complete verification environment for the ATM based FPGA. Responsibility was Packet Generation. ATM (AAL 1) Headers generation. PRBS pattern generation. Verification environment development. Testcase coding, execution and desgin debug.
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Verification EngineerWipro Limited May 2002 - Oct 2002Bangalore, Karnataka, InThe project involved the development, simulation and verification of architectural model of the ARM based Telematics gateway Soc in C. The simulation results were used for analyzing the functionality and performance of the ASIC.Responsibility involved Development of peripheral models, system level simulation and verification. Development of cycle accurate behavioral models of peripherals like Uart, Ssp ,Generic Sram,Generic AHB and Generic APB modules used in the SoC. Simulation and functional verification of the integrated system. Support for the proprietary C modeling simulation tool. Developed the AMBA transaction functions for the simulation tool.
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Verification EngineerWipro Limited Jan 2002 - Apr 2002Bangalore, Karnataka, InThe project involved design and development of a complete c platform where the c based hardware modules can be run. Responsibilities were to schedule the different c based hardware modules, generate vcd file and come up with an efficient user interface for user module integration. The c platform supports the scheduling of the modules, interrupt generation, different clock frequency generation, etc… There is no HDL simulator dependency for this platform.
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Verification EngineerWipro Limited Jun 2001 - Dec 2001Bangalore, Karnataka, InThe Project involved Design of an Automated Verfication Environment. An Automated verification Environment, where C testcases as independent programs can be seamlessly integrated to any hardware simulator. Responsibilites were to develop a C environment for writing the testcases. The testcase were to be integrated automatically to any HDL simulator. Wrote perl scripts to generate makefile(s) and for automatic compilations of the files. The perl script generates makefiles for many languages (VHDL/verilog/C).
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Design EngineerWipro Limited Jan 2001 - May 2001Bangalore, Karnataka, InThe project involved the design and testing of Dataflow module, part of a Network Processor.Played role as a Design Engineer of Traffic Generator and 32 bit CRC generator. The Traffic Generator generates PRIZMA Cell traffic, which is an IP format. The Traffic Generator was to be used as an external traffic generator so as to generate the traffic for the Dataflow module and test it.
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Verification EngineerWipro Limited Jun 2000 - Dec 2000Bangalore, Karnataka, InThis ASIC had various datflow components and was part of a Network Dataprocessing module. Was involved in testbench creation, verification models, test plan, testcases, and functional coverage matrix generation
Md Basharat Ali Skills
Agile Project Management
Verilog
Vhdl
System Verification
Vmm
Perl
Ocaml
Python
Gnu Make
Usb
Pcie
C
C++
Ahb
Amba Ahb
Md Basharat Ali Education Details
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Birla Institute Of Technology And Science, PilaniElectrical And Electronics Engineering -
Birla Institute Of Technology And Science, PilaniElectronics And Communications Engineering
Frequently Asked Questions about Md Basharat Ali
What company does Md Basharat Ali work for?
Md Basharat Ali works for Intel Corporation
What is Md Basharat Ali's role at the current company?
Md Basharat Ali's current role is Verification Lead at Intel Corporation.
What is Md Basharat Ali's email address?
Md Basharat Ali's email address is ba****@****pro.com
What schools did Md Basharat Ali attend?
Md Basharat Ali attended Birla Institute Of Technology And Science, Pilani, Birla Institute Of Technology And Science, Pilani.
What skills is Md Basharat Ali known for?
Md Basharat Ali has skills like Agile Project Management, Verilog, Vhdl, System Verification, Vmm, Perl, Ocaml, Python, Gnu Make, Usb, Pcie, C.
Who are Md Basharat Ali's colleagues?
Md Basharat Ali's colleagues are Marie Conte, Anthony Wong, Kim Erpelding, Bart Corsey, Sergei Nesterov, Lauren Tippets, Grettchen Salas.
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