Md Basharat Ali Email & Phone Number

Santa Clara, California, Us

Bangalore, Karnataka, In

Verification of SOC, with integration of various custom blocks. A Configurable SOC architecture , for a semi conductor lead company.

Bangalore, Karnataka, In

Lead a verification team and drive the project to closure on verification aspects. Help the team in technical issues both with coding and debugging of the design. Plan verification activities, assign resources, and track the progress of the project. Report the status on the project to the client.

Bangalore, Karnataka, In

Verification of a complex engine block, in UVM methodology from scratch. Development of test plan, coding of test bench, test cases, regression, bug tracking, reviews, profiling, coverage, etc. Complete randomization of environment, including uvm register package.

Bangalore, Karnataka, In

The project was for functional verification of a complex architecture to support dataflow between different interfaces which includes USB (HUB, Host, Endpoint), SD card. Its a MIPS based system, with the SOC having support for differnt securities. Responsibilities: To make the verification strategy, verification plan, Regression scripts, Project Management, Test bench Buildup, Debugging of the design, C based programming of test cases.

Bangalore, Karnataka, In

The project was to validate the VCS tool from Synopsys Inc. Responsibilities: To make the validation plan, run different designs on vcs tool, and make the existing test cases pass in the designs, using the new debug features of VCS.

Bangalore, Karnataka, In

The Project was for functional verification of USB and it’s integration into an ASIC. The ASIC had a Synopsys USB OTG Core. The work revolved around testing the USB connectivity by doing different transfers, and USB protocols, there by verifying the functionality, and targeting the different memories in the ASIC. Responsibilities: Complete Ownership in verification of USB connectivity, and functional verification of the ASIC with USB fuctionality. C based programming for USB transfers. Test plan, testcases, coverage, etc. Leading a team to guide their areas of work in verification of this ASIC.

Bangalore, Karnataka, In

Project was to design and develop the verification IP model of PCIe. Responsible as a Project Lead was to train the team on PCIe, system verilog and come up with the architecture for VIP development.

Bangalore, Karnataka, In

The project was for functional verification of USB and PCIe interface modules. The SOC had USB and PCIe IP-Core modules, and was developing interfaces to these cores.Responsibilities: To make module level testbench environment for USB and PCIe interface modules. The Interface modules would be the bridge between USB/PCIe and the SOC. Make the test plan, write testbench components using Denali verification models, write testcases, and generate coverage reports, for both module level and system level environments.

Bangalore, Karnataka, In

The project was to execute benchmarks on Cortex A8 model, and tweak the cycle wait states, with numbers from RTL.

Bangalore, Karnataka, In

The project was to model the Cortex A8 processor, and use it as the golden reference model for verification. Responsibilities: was involved in modeling the complete Cortex A8 processor, with instruction set encoding (ARM, Thumb, Thumb-2, and later on support Neon instructions), Memory Manangement Module (VA to PA, security checks, L1-I and D Caches), Trustzone features, CoProcessor Module.Debugged the Trustzone suite of Assembly test cases, and supported the ISS (Instruction set simulator).

Bangalore, Karnataka, In

The Superscalar, Dual issue ARM V7 Architecture based core is used for a Real time embedded application. Proect was to Support Darwin tool, to generate the controlled random test cases for Tiger processor. Involved in the Darwin team, which developed the Darwin tool to generate controlled random test case to test the processor. Involved in generating the combination of Functional points to generate the hit/miss matrix, based on which the test case worthiness would be decided.

Bangalore, Karnataka, In

The Project was to develop clock accurate model of the three FPGAs supported for the PON architecture. The system models developed are used as golden reference in the verification environment. The system environment (involving only the system models) was to be used for study and analysis. The verification was done using Vera where the System-models were integrated with RTL written in Verilog, and test cases in Vera. Responsibility : Architecting the system models hierarchy and integration. Design and Development of MAC layer. Integration of models with the RTL environment for three FPGAs. Platform development for system Co-verification. Generation of system reports for analysis. Verification using Test cases written in Vera.

Bangalore, Karnataka, In

The project was to develop complete verification environment for the ATM based FPGA. Responsibility was Packet Generation. ATM (AAL 1) Headers generation. PRBS pattern generation. Verification environment development. Testcase coding, execution and desgin debug.

Bangalore, Karnataka, In

The project involved the development, simulation and verification of architectural model of the ARM based Telematics gateway Soc in C. The simulation results were used for analyzing the functionality and performance of the ASIC.Responsibility involved Development of peripheral models, system level simulation and verification. Development of cycle accurate behavioral models of peripherals like Uart, Ssp ,Generic Sram,Generic AHB and Generic APB modules used in the SoC. Simulation and functional verification of the integrated system. Support for the proprietary C modeling simulation tool. Developed the AMBA transaction functions for the simulation tool.

Bangalore, Karnataka, In

The project involved design and development of a complete c platform where the c based hardware modules can be run. Responsibilities were to schedule the different c based hardware modules, generate vcd file and come up with an efficient user interface for user module integration. The c platform supports the scheduling of the modules, interrupt generation, different clock frequency generation, etc… There is no HDL simulator dependency for this platform.

Bangalore, Karnataka, In

The Project involved Design of an Automated Verfication Environment. An Automated verification Environment, where C testcases as independent programs can be seamlessly integrated to any hardware simulator. Responsibilites were to develop a C environment for writing the testcases. The testcase were to be integrated automatically to any HDL simulator. Wrote perl scripts to generate makefile(s) and for automatic compilations of the files. The perl script generates makefiles for many languages (VHDL/verilog/C).

Bangalore, Karnataka, In

The project involved the design and testing of Dataflow module, part of a Network Processor.Played role as a Design Engineer of Traffic Generator and 32 bit CRC generator. The Traffic Generator generates PRIZMA Cell traffic, which is an IP format. The Traffic Generator was to be used as an external traffic generator so as to generate the traffic for the Dataflow module and test it.

Bangalore, Karnataka, In

This ASIC had various datflow components and was part of a Network Dataprocessing module. Was involved in testbench creation, verification models, test plan, testcases, and functional coverage matrix generation

Master Of Science (M.S.), Electrical And Electronics Engineering

Bachelor'S Degree, Electrical, Electronics And Communications Engineering