Technology Proficiency: Experience in designing full custom SRAM memory layouts for advanced technologies, including GAAFET and FINFET, across various nodes such as Intel 18A and SS8.SRAM Memory Compilers: Specialized in creating layouts for various blocks within SRAM memory compilers.Critical Block Design: Proficient in designing critical blocks.Instance Level Checks: I perform instance-level checks like DRC, LVS, ERC, and EMIR to ensure design accuracy and reliability.Release Phases: Successfully navigated through multiple release phases, including LEF release, test chip GDS release, and full compiler release.ECO Implementation: Experienced in assessing feasibility and implementing Electrical Change Orders (ECO) in designs.