I have a PhD in Electrical and Computer Engineering with an expertise in circuit design and an emphasis in ASIC and FPGA design. During the past three years of my career, I worked at Tennessee State University as an Assistant Professor where I conducted research, guided and motivated students in different circuit design projects. My design capabilities have been enriched through my work at IBM, at Oak Ridge National Lab and at Transwitch Corp. My experience includes: • Integrated Circuit (IC) design flow that includes design capture, schematic simulation, physical layout, DRC, net-list extraction, LVS check, pad design, tape out GDSII, prototype fabrication and testing etc. using EDA tools such as Cadence and Tanner tools. • ASIC design capture, simulation, synthesis, placement and routing, timing analysis, verification and implementation on FPGA using VHDL/Verilog HDL. • Hands-on experience in lab testing equipments.• Device model, simulation, testing and SPICE parameter extraction for CAD tools.Design Tools Skills: • Cadence digital and analog design environment CAD tools, Tanner EDA tools.• Modelsim, Synopsis, Design Analyzer, Xilinx tools. • MEDICI (synopsys TCAD) device simulator, ATLAS device simulator.• HSPICE, OrCAD PSPICE, T-SPICE, Multisim, Ultiboard, ADS. • ASITIC (Design of LC-VCO using on-chip inductor model extracted from CAD tools ASITIC) • Design and stress analysis a food rationing tray using SolidWorks and Femlab • Eins Timer, Eins Tuner and TLT for timing analysis for different critical paths Programming Languages: • C/C++, Matlab (for calculation and evaluation of analytical model, circuits and systems) • VHDL, Verilog RTL, Perl, LabVIEW Measuring Instruments: Parameter analyzer (HP4145/4156A), CV analyzer (Keithley 590/595), probe station, precision LCR meter, spectrum analyzer, network analyzer (HP3589A), Signatone thermal probing systemsSpecialties: Analog and Digital Circuit DesignCustom ASIC and FPGA Design FlowKnowledge of Cadence CAD Tools