Mark Divito Email and Phone Number
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Digital ASIC Hardware Design Engineer and Manager- Proven success as designer for high-volume SoC products (200 million+ units)- Chip lead and designer for high-speed automotive communications products- Design expertise in RTL design, SoC integration, verification, serial communication and data integrity, digital video interface protocols, security hardware IPs- Success architecting and designing new IPs, managing cross-functional teams, and leading projects across multiple locations- Proponent of design and methodologies to promote scalability, robustness, and ease of use
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Senior Manager, Mixed Signal Design Engineering (Digital Design)Analog Devices Aug 2021 - PresentWilmington, Ma, UsDigital IC Design Engineer and Manager- GMSL SerDes product line- High-speed communication design for automotive ADAS and infotainment markets- Chip lead for several high-volume GMSL products (30 million+ units)- Manage a team of digital design and verification engineers, covering 10+ active IC design projects with $200 million+ in lifetime revenue- Design and management responsibilities for high-speed digital communications, video transmitters and receivers (MIPI CSI DPHY/CPHY, HDMI, eDP, oLDI), I2C, UART, SPI, GPIO, Ethernet/RGMII, data integrity and CRC/ECC, functional safety (ASIL)- Leadership and technical work across every aspect of design process: product architecture, RTL design, functional and gate-level verification, timing and power analysis, bench validation, ATE bringup, product introduction, and mass production- Proven success architecting and designing new IPs, managing cross-functional teams, and driving digital methodology improvements for scalability, verification coverage, bench automation, and reduced design cycle times
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Manager, Ic DesignMaxim Integrated Sep 2020 - Aug 2021San Jose, Ca, UsDigital IC Design Engineer and Manager- GMSL SerDes product line- High-speed communication design for automotive ADAS and infotainment markets- Chip lead for several high-volume GMSL products (30 million+ units)- Manage a team of digital design and verification engineers, covering 10+ active IC design projects with $200 million+ in lifetime revenue- Design and management responsibilities for high-speed digital communications, video transmitters and receivers (MIPI CSI DPHY/CPHY, HDMI, eDP, oLDI), I2C, UART, SPI, GPIO, Ethernet/RGMII, data integrity and CRC/ECC, functional safety (ASIL)- Leadership and technical work across every aspect of design process: product architecture, RTL design, functional and gate-level verification, timing and power analysis, bench validation, ATE bringup, product introduction, and mass production- Proven success architecting and designing new IPs, managing cross-functional teams, and driving digital methodology improvements for scalability, verification coverage, bench automation, and reduced design cycle times -
Senior Member Of Technical Staff, Ic DesignMaxim Integrated Sep 2017 - Sep 2020San Jose, Ca, UsDigital IC Design Engineer - High-speed GMSL SerDes product line - Architecting and specifying digital sections of complex mixed signal ICs, including high speed serial interfaces and solutions for routing and aggregation of video data - RTL design - Test bench development - Functional and gate-level verification - Timing analysis - Power consumption and power integrity analysis
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Senior EngineerQualcomm Jun 2012 - Aug 2017San Diego, Ca, UsDigital ASIC Hardware Design Engineer - Own and drive IP designs, from spec to RTL logic design to implementation - Current work in Security Hardware IP core development. Implement and deliver cores to 5 -10 Snapdragon and mobile chipset products yearly, across all product tiers. - Design and integration of new cores and subsystems, successful and fully functional first time in silicon, at latest process node - RTL design and implementation using low power techniques, multiple power domains, multiple clock domains, and leading-edge process nodes - Implementation experience performing power aware synthesis, formal verification, static timing analysis closure, and ECOs - Block level verification with SystemVerilog/UVM, power aware simulations, formal verification. SoC level verification with SystemVerilog and C. Silicon bring up and debug experience. - Drive SoC and VLSI methodology initiatives, plan and implement integration flow enhancements - Subsystem and SoC integration, schedule and deliverables, and technical documentation - Coordinate across many teams and levels, including software, verification, physical design. Serve as IP core’s single point of contact while supporting production testing and ramp-up. -
Digital Design EngineerTexas Instruments May 2011 - Aug 2011Dallas, Tx, UsSummer internship - Digital design engineer for custom mixed-signal ASICs - All phases of design flow, from RTL design to synthesis and static timing analysis to physical layout - Also performed pre-silicon verification, code coverage, and created test bench environment - Silicon lab testing and spec validation of ASIC parts - High volume mixed signal ASICs used in Apple and IBM products -
Branch ManagerHertz Nov 2006 - Jan 2010Estero, Fl, UsBranch Manager of a Hertz Local Edition car rental location - Hired, trained, and lead a team of employees, with full responsibility for their performance and promotion - Created 17% quarterly revenue growth and achieved monthly expenditure goals - Presented business proposals and closed deals with executive-level management and medium sized business owners; commitments ranging from $2000 to $150,000 per year - Performed sales presentations to prospective accounts, and became the account manager for each - Created a multi-branch marketing plan which captured 33% market share within 6 months in new territory
Mark Divito Skills
Mark Divito Education Details
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University Of Illinois Urbana-ChampaignElectrical And Electronics Engineering -
William & MaryPolitical Science And Government
Frequently Asked Questions about Mark Divito
What company does Mark Divito work for?
Mark Divito works for Analog Devices
What is Mark Divito's role at the current company?
Mark Divito's current role is Senior IC Design Manager at Analog Devices (Digital Design Engineer).
What is Mark Divito's email address?
Mark Divito's email address is ma****@****ted.com
What schools did Mark Divito attend?
Mark Divito attended University Of Illinois Urbana-Champaign, William & Mary.
What skills is Mark Divito known for?
Mark Divito has skills like Computer Engineering, Computer Hardware, Asic, Logic Design, Wireless, Hardware, Security, Vlsi, Ic, Verilog, Systemverilog, Vhdl.
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