Mark D'Souza

Mark D'Souza Email and Phone Number

Sr Director Product Development Engineer; Data Center GPU and Accelerated Processing Business Unit at AMD @ AMD
Sunnyvale, California
Mark D'Souza's Location
Austin, Texas, United States, United States
Mark D'Souza's Contact Details

Mark D'Souza personal email

n/a

Mark D'Souza phone numbers

About Mark D'Souza

Director Product Development Engineering responsible for Platform Silicon EngineeringSuccessful record of driving organizational success through solutions across Product Design, Manufacturing Operations, Quality and Customer Relations. Driving business process improvements leading to multi-million dollar cost savings. Ramped products and shipped over tens of millions of units to date. Extensive expatriate working experience in Asia.QUALIFICATIONS• Product/Program Management • Product Development • Silicon Debug • Operational Excellence • Change Management • Margin Improvement • Inventory Optimization • Out-sourced Manufacturing • Cost Optimization • High Performance Team Building • International Management • Mentoring and CoachingCAREER HIGHLIGHTS• Ramped SOC powering a Game console in 2013, shipping tens of millions of units for hundreds of millions of revenue for AMD. Successfully negotiated NRE, pricing, SOW & supply agreements with Microsoft. • Selected to serve as Chief of Staff for three CEO’s working with BOD & C-suite providing oversight and guidance on a variety of issues.• Restructured the Asia Engineering organization from a functional to a product focused group. Established foundation for Asia Product Development team in Singapore and China, hiring leadership for both sites.• Secured ~$2M from Singapore Economic Development Board to support product development in Singapore.• Implemented cost reduction efforts for Athlon family of products including Burn-in elimination, Test insertion removal, and performance locking across all Athlon products that virtually eliminated all re-marking and selling of Athlons in the gray market.

Mark D'Souza's Current Company Details
AMD

Amd

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Sr Director Product Development Engineer; Data Center GPU and Accelerated Processing Business Unit at AMD
Sunnyvale, California
Website:
amd.com
Mark D'Souza Work Experience Details
  • Amd
    Sr Director Product Dev Engineer; Customer Engineering For Cloud Gaming And Vdi Business Unit
    Amd Aug 2020 - Present
    Santa Clara, California, Us
  • Amd
    Sr Director Product Development Engineer; Rtg Platform Engineering
    Amd Nov 2017 - Aug 2020
    Santa Clara, California, Us
    Responsible for Platform Silicon Engineering for Radeon Technology Group
  • Amd
    Director Of Product Development Engineering
    Amd Jun 2016 - Aug 2020
    Santa Clara, California, Us
    Responsible for Platform Emulation and System Debug.
  • Amd
    Director Product Management (Game Console)
    Amd Sep 2012 - Jun 2016
    Santa Clara, California, Us
    Responsible for profit and loss (P&L) and daily operations for Microsoft Semi-Custom business. Drove activities from NPD through IP and HVM.- post-silicon validation, proto deliveries, cost optimization and product ramp. Consistently met quarterly revenue and margin targets. Represent Microsoft’s interests to design, product, and supply chain & quality teams. Primary interface with customer for contract negotiations, supply, pricing and Silicon Engineering needs• Manage supply and inventory across Foundries to meet steep demand optimizing revenue and margin.• Spearhead successful excursion management with no impact to customer¡¦s stringent quality levels.• Lead active engagement with customer on future product definition and specifications.• Engage with foundry partners to drive future process technology ramps.• Responsible for quality-related communication; ensure issues are resolved and controls in place to prevent recurrence.• Accompanied customer on all Audits to internal factories, foundries and OSAT; followed through on all actions.• Responsible for PCN communication and managing customer expectations to the change.• Active participation in pre-silicon and post silicon, bump and package debug
  • Amd
    Chief Of Staff To The Ceo
    Amd Jan 2010 - Sep 2012
    Santa Clara, California, Us
    Worked directly for three CEO’s supporting AMD executive team (AET) and key functions across the company to align strategy and action in support of corporate goals and objectives. • On-boarded new CEOs, serving as sounding board for emerging issues, problems and opportunities.• Responsible for facilitating and managing monthly Executive Team and Operations meetings.• Developed content for CEO presentations, executive reports and summaries for BOD, customers and partners.• Managed pre-meeting preparation for CEO’s key meetings and follow up on post-meeting actions.• Represented CEO interests at various AMD initiatives including AMD NextGen Engineer program advocating for stronger and more interactive engineering education at K-12 thru college levels, and corporate responsibility.
  • Amd
    Director Product Development/Operations Engineering (Expatriate Assignment In Singapore)
    Amd Jan 2007 - Jan 2010
    Santa Clara, California, Us
    Responsible for leading AMD Product Development Teams, Device Analysis and Rerliability teams (~300) in Singapore and Suzhou, China. Teams are responsible for customer samples deliveries, silicon design characterization and debug, failure analysis, product qualification and day to day production operations support. Led efforts to optimize manufacturing cost through yield improvement, flow optimization, test time reduction efforts and Lean CIP.• Restructured the Asia Engineering organization from a functional to a product focused organization enabling parallel issues resolution across different product families. • Established a dedicated production support team, and identified and placed key individuals in leadership positions. All was accomplished without disrupting day to day operations.• Instituted the factory SCT (Silicon Core Team) concept to support manufacturing readiness, product launches and volume manufacturing. New concept was piloted on major CPU product in 2007 and is now being successfully applied to all products across both sites. • Engaged with Singapore Economic development Board and secured funding to sponsor AMD development projects in Singapore.
  • Amd
    Department Manager, Product Dev, Engineering Silicon Development And Debug
    Amd Jun 2002 - Feb 2007
    Santa Clara, California, Us
    Managed and led the Center of Excellence for Silicon Development and Debug in Austin and Singapore. Organization was responsible for ensuring all data sheet specifications for AMD CPU products performed through ATE/System level characterization, debug and qualification.• Implemented cost reduction efforts like Burn-in elimination and Test insertion removal. Also implemented performance locking across all Athlon products that virtually eliminated all re- marking and selling of Athlons in the gray market. Successfully transferred all Athlon products to embedded team for End of life support.
  • Amd
    Member Of Technical Staff
    Amd Feb 2000 - Jun 2002
    Santa Clara, California, Us
    Leadership role on AMD’s first 130nm product from design tape out to high volume production release• Developed the “Productization” concept where a dedicated team is responsible for key aspects of product introduction such as qualification, characterization and debug, samples and customer support and volume production; allowing early engagement of engineering and manufacturing teams for seamless transition to volume production. This laid the foundation for future development teams.
  • Amd
    Fab Product Engineering Supervisor
    Amd Oct 1994 - Jan 2000
    Santa Clara, California, Us
    Established and managed the Fab 25 Failure analysis team which was responsible for failure and yield analysis for all AMD CPU products across exiting and new process technologies.• Set up the first automated Bitmap failure analysis navigation capability on a dual beam FIB. Developed new stripback recipes and techniques for deprocessing C4 and multiple metal layer wafers. Led several Tiger teams and participated in several cross functional team to resolve yield and product issues
  • Amd
    Product Engineering Cfm & Product Engineering
    Amd Nov 1993 - Oct 1994
    Santa Clara, California, Us
    Part of bring up team for fab25, AMD’s first 8 inch fabrication facility. One of 5 engineers assigned to the Submicron Development Center (SDC) to support startup through development in Contamination Free Manufacturing (CFM) and Product Engineering disciplines
  • Maxim Integrated Products
    Reliability Engineer
    Maxim Integrated Products Jan 1993 - Nov 1993
    San Jose, Ca, Us
    Responsible for planning and execution of product, package and process qualifications for new product releases. Developed FA techniques for defect isolation. Identified two unique defect mechanisms; first resulted in temporary shutdown of production fab and the second drove a product redesign.
  • Arnet Corporation
    Product Engineer
    Arnet Corporation Oct 1989 - Jul 1990
    Testing Hardware and debug.

Mark D'Souza Skills

Semiconductors Product Engineering Cross Functional Team Leadership Product Management Program Management Product Development Debugging Manufacturing Testing Silicon Engineering Management Ic Lean Manufacturing Failure Analysis Soc Strategy Semiconductor Industry Management Processors Microprocessors Asic Leadership Start Ups Organizational Development Manufacturing Operations Management Reliability International Management Embedded Systems Strategic Partnerships Manufacturing Management System Architecture Engineering Product Marketing Electronics Mentoring And Coaching Project Management Analog P&l Management P&l Responsibility Contract Management Hardware Architecture Operational Excellence Out Sourced Manufacturing Highperformance Team Building Collaborative Relationship Development Change Managemen Functional Program Management Manufacturing Operations Mixed Signal Product Launch High???performance Team Building

Mark D'Souza Education Details

  • Florida Institute Of Technology
    Florida Institute Of Technology
    Electrical Engineering
  • Tennessee State University
    Tennessee State University
    Electrical Engineering
  • New Indian School Kuwait
    New Indian School Kuwait

Frequently Asked Questions about Mark D'Souza

What company does Mark D'Souza work for?

Mark D'Souza works for Amd

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Mark D'Souza's current role is Sr Director Product Development Engineer; Data Center GPU and Accelerated Processing Business Unit at AMD.

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Mark D'Souza attended Florida Institute Of Technology, Tennessee State University, New Indian School Kuwait.

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Mark D'Souza has skills like Semiconductors, Product Engineering, Cross Functional Team Leadership, Product Management, Program Management, Product Development, Debugging, Manufacturing, Testing, Silicon, Engineering Management, Ic.

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Mark D'Souza's colleagues are Leo Reyes, Trishali Reddy Chilmula, Vipula Sharma, Devubha Sodha, Edward Lee, Kavana Reddy Raja Reddy, Amit J..

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