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HDL / HVL : Verilog HDL, System VerilogMethodologies :UVM, OVMExpertise : SOC/IP Design Verification, Behavior/Architectural modeling, Logic SimulationEDA Tool(s): Synopsys (VCS), Cadence Incisive Manager, ICCR, vplanner, Emanager, Incisive Metrics Centre, Verdi, Model Sim (QuestaSim), Jasper (AFL, FPV, UNR & Connectivity apps)Version Control Systems: CVS, DesignSync, ClearCase, GIT, SVN
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Soc Design Verification ManagerApple Oct 2019 - PresentCupertino, California, Us -
Principal Verification EngineerNxp Semiconductors Jan 2017 - Oct 2019Eindhoven, Noord-Brabant, Nl -
Principal Design EngineerBroadcom Inc. Apr 2015 - Dec 2016Palo Alto, California, Us -
Senior Staff Design EngineerBroadcom Inc. Sep 2013 - Apr 2015Palo Alto, California, UsWorked on various Wireless SOCs including NFC , 60Ghz -
Engineer IiiQualcomm Jan 2013 - Sep 2013San Diego, Ca, UsWorked on Sub-System and Chip level verification for Peripherals for eg. USB, SPI, I2C etc -
Staff Design EngineerFreescale Semiconductor Jul 2012 - Jan 2013Austin, Texas, UsWorked on verification of various IPs, e.g. Display Controller Unit, System Status and Configuration Module etc. ,at block level for a SOC, which includes Functional Model designs, verification environment, writing Test Plans and Testcases in UVM. -
Senior Design EngineerFreescale Semiconductor Sep 2010 - Jul 2012Austin, Texas, UsWorked on verification of various IPs at block level for a SOC, which includes Functional Model designs, verification environment, writing Test Plans and Testcases in UVM -
Design ManagerPerfectus Inc. Dec 2007 - Sep 2010Managed and worked on developing Verification IPs. Pre and Post sales activities of the Verification IP packages. Deployment of VIPs at customer end, bringing up of verification environment in OVM and helping customer develop testcases.
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Design And Verification EngineerMicrochip Technology Apr 2007 - Nov 2007Chandler, Az, UsRTL Modifications to the Top level module, IOMUX and Pads as per the specification. Peripheral Integration as per design specifications. Modifying the existing testbench and Debugging failing test patterns for RTL. Debugging gate level netlist after Post Layout. Running Spyglass and Modelsim for linting purpose and checking floating nodes in the design. Performing ECOs on netlist. -
Member Technical StaffPerfectus Technology Inc. Jun 2006 - Apr 2007- Member of design & verification group- Worked on several SOC/ASIC verification projects ex. mobile application SOC etc- Worked on development of Verification IPs & Design IPs for various interface protocols ex. SAS Expander, SMBus Master Controller etc
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Design EngineerNsys Design Systems Pvt. Ltd. Jun 2005 - Jun 2006- Member of Design & Verification team. - worked on development of Verification IPs for several interface protocols ex. PCI, PCIe, PCIe-PCI/X bridge, SMBus, APB, AXI
Mehul Kumar Skills
Frequently Asked Questions about Mehul Kumar
What company does Mehul Kumar work for?
Mehul Kumar works for Apple
What is Mehul Kumar's role at the current company?
Mehul Kumar's current role is SoC Design Verification Manager.
What is Mehul Kumar's email address?
Mehul Kumar's email address is ku****@****ail.com
What skills is Mehul Kumar known for?
Mehul Kumar has skills like Systemverilog, Ncsim, Modelsim, Verilog, Vcs, Debugging, Ahb, Functional Verification, Pcie, Vlsi, Usb, Coverage Analysis.
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