1. Leader of module level design spec flow team, led and together with teammates implemented new generation of design spec flows.2. Exemplify doing RTL design for first batch of modules which are compliant to new architecture and alone built verification environment using UVM for the new architecture which greatly helped both Design and DV team to establish the new methodology in short period of time.3. Designer of some IQ modules HW micro-Architecture base on system algorithm, perform timing analysis, area analysis, RTL power analysis and performance analysis. Experience various design tools including Verdi debug tool, lint check tool, CDC check and PowerArtist and etc.4. Core owner of a processing engine of camera sub-system, integrated 30+ sub-modules5. Performed area & power & timing optimizations of some IQ modules and common components through micro-architecture improvement and power artist analysis which helped saved up to 50% ram power, 30% area and 25% performance for some modules.6. Achieved 100% verification quality of owned modules by setup random-constraints, complete test plan, create tests, assertion check and close functional & code coverage.7. Bring up core level verification features and built common components including performance checker for DV team by developing UVM sequence, agents, monitors and etc.

Performed formal verification on AHB/AXI bus and memory redundancy of camera subsystem, including infrastructure building, assertion closure, etc..

FPGA design to build next generation of asynchronous electronic acquisition system for matrix flat-pannel imager by using Xilinx Virtex board and ISim tool.